diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index cc2469f8c29..a9d41325de7 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -2946,6 +2946,8 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
   // of optional arguments is implemented.
   if (Opcode == ARM::CPS3p) {
     // Let's reject impossible imod values by returning false.
+    // AsmPrinter cannot handle imod=0b00, plus (imod=0b00,M=1,iflags!=0) is an
+    // invalid combination, so we just check for imod=0b00 here.
     if (slice(insn, 19, 18) == 0 || slice(insn, 19, 18) == 1)
       return false;
     MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 18))); // imod
diff --git a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
new file mode 100644
index 00000000000..5202217b6a7
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
@@ -0,0 +1,4 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# invalid (imod, M, iflags) combination
+0x93 0x1c 0x02 0xf1
diff --git a/test/MC/Disassembler/ARM/invalid-VLDMSDB-arm.txt b/test/MC/Disassembler/ARM/invalid-VLDMSDB-arm.txt
new file mode 100644
index 00000000000..f57ddbcafd6
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-VLDMSDB-arm.txt
@@ -0,0 +1,4 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# core registers out of range
+0xa5 0xba 0x52 0xed