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ARM allow Q registers in vldm/vstm register lists.

Browse Source 
rdar://9672822

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-11-11 21:27:40 +00:00
parent 6fd98ae7ef
commit ce485e7f70
2 changed files with 47 additions and 27 deletions
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72
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -2410,6 +2410,29 @@ static unsigned getNextRegister(unsigned Reg) {
}
}
// Return the low-subreg of a given Q register.
static unsigned getDRegFromQReg(unsigned QReg) {
switch (QReg) {
default: llvm_unreachable("expected a Q register!");
case ARM::Q0: return ARM::D0;
case ARM::Q1: return ARM::D2;
case ARM::Q2: return ARM::D4;
case ARM::Q3: return ARM::D6;
case ARM::Q4: return ARM::D8;
case ARM::Q5: return ARM::D10;
case ARM::Q6: return ARM::D12;
case ARM::Q7: return ARM::D14;
case ARM::Q8: return ARM::D16;
case ARM::Q9: return ARM::D19;
case ARM::Q10: return ARM::D20;
case ARM::Q11: return ARM::D22;
case ARM::Q12: return ARM::D24;
case ARM::Q13: return ARM::D26;
case ARM::Q14: return ARM::D28;
case ARM::Q15: return ARM::D30;
}
}
/// Parse a register list.
bool ARMAsmParser::
parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
@ -2425,6 +2448,16 @@ parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
if (Reg == -1)
return Error(RegLoc, "register expected");
// The reglist instructions have at most 16 registers, so reserve
// space for that many.
SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
// Allow Q regs and just interpret them as the two D sub-registers.
if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
Reg = getDRegFromQReg(Reg);
Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
++Reg;
}
const MCRegisterClass *RC;
if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
@ -2435,10 +2468,7 @@ parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
else
return Error(RegLoc, "invalid register in register list");
// The reglist instructions have at most 16 registers, so reserve
// space for that many.
SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
// Store the first register.
// Store the register.
Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
// This starts immediately after the first register token in the list,
@ -2452,6 +2482,9 @@ parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
int EndReg = tryParseRegister();
if (EndReg == -1)
return Error(EndLoc, "register expected");
// Allow Q regs and just interpret them as the two D sub-registers.
if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
EndReg = getDRegFromQReg(EndReg) + 1;
// If the register is the same as the start reg, there's nothing
// more to do.
if (Reg == EndReg)
@ -2476,6 +2509,12 @@ parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Reg = tryParseRegister();
if (Reg == -1)
return Error(RegLoc, "register expected");
// Allow Q regs and just interpret them as the two D sub-registers.
bool isQReg = false;
if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
Reg = getDRegFromQReg(Reg);
isQReg = true;
}
// The register must be in the same register class as the first.
if (!RC->contains(Reg))
return Error(RegLoc, "invalid register in register list");
@ -2489,6 +2528,8 @@ parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Reg != OldReg + 1)
return Error(RegLoc, "non-contiguous register range");
Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
if (isQReg)
Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
}
SMLoc E = Parser.getTok().getLoc();
@ -2500,29 +2541,6 @@ parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return false;
}
// Return the low-subreg of a given Q register.
static unsigned getDRegFromQReg(unsigned QReg) {
switch (QReg) {
default: llvm_unreachable("expected a Q register!");
case ARM::Q0: return ARM::D0;
case ARM::Q1: return ARM::D2;
case ARM::Q2: return ARM::D4;
case ARM::Q3: return ARM::D6;
case ARM::Q4: return ARM::D8;
case ARM::Q5: return ARM::D10;
case ARM::Q6: return ARM::D12;
case ARM::Q7: return ARM::D14;
case ARM::Q8: return ARM::D16;
case ARM::Q9: return ARM::D19;
case ARM::Q10: return ARM::D20;
case ARM::Q11: return ARM::D22;
case ARM::Q12: return ARM::D24;
case ARM::Q13: return ARM::D26;
case ARM::Q14: return ARM::D28;
case ARM::Q15: return ARM::D30;
}
}
// parse a vector register list
ARMAsmParser::OperandMatchResultTy ARMAsmParser::
parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {

2
test/MC/ARM/simple-fp-encoding.s
View File

@ -229,8 +229,10 @@
@ CHECK: vstmia r1, {d2, d3, d4, d5, d6, d7} @ encoding: [0x0c,0x2b,0x81,0xec]
@ CHECK: vstmia r1, {s2, s3, s4, s5, s6, s7} @ encoding: [0x06,0x1a,0x81,0xec]
@ CHECK: vpush {d8, d9, d10, d11, d12, d13, d14, d15} @ encoding: [0x10,0x8b,0x2d,0xed]
vstmia r1, {d2,d3-d6,d7}
vstmia r1, {s2,s3-s6,s7}
vstmdb sp!, {q4-q7}
@ CHECK: vcvtr.s32.f64 s0, d0 @ encoding: [0x40,0x0b,0xbd,0xee]
@ CHECK: vcvtr.s32.f32 s0, s1 @ encoding: [0x60,0x0a,0xbd,0xee]