6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-06 09:44:39 +00:00
Code Issues Projects Releases Wiki Activity

Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to

Browse Source 
t2LDREX/t2STREX instructions.  Add two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128293 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-03-25 18:29:49 +00:00
parent 8b2b43c41d
commit ceceabd4b1
2 changed files with 12 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
View File

@ -1194,8 +1194,8 @@ static bool DisassembleThumb2LdStEx(MCInst &MI, unsigned Opcode, uint32_t insn,
OpIdx = 0;
assert(NumOps >= 2
&& OpInfo[0].RegClass == ARM::GPRRegClassID
&& OpInfo[1].RegClass == ARM::GPRRegClassID
&& OpInfo[0].RegClass > 0
&& OpInfo[1].RegClass > 0
&& "Expect >=2 operands and first two as reg operands");
bool isStore = (ARM::t2STREX <= Opcode && Opcode <= ARM::t2STREXH);
@ -1205,25 +1205,25 @@ static bool DisassembleThumb2LdStEx(MCInst &MI, unsigned Opcode, uint32_t insn,
// Add the destination operand for store.
if (isStore) {
MI.addOperand(MCOperand::CreateReg(
getRegisterEnum(B, ARM::GPRRegClassID,
getRegisterEnum(B, OpInfo[OpIdx].RegClass,
isSW ? decodeRs(insn) : decodeRm(insn))));
++OpIdx;
}
// Source operand for store and destination operand for load.
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
decodeRd(insn))));
++OpIdx;
// Thumb2 doubleword complication: with an extra source/destination operand.
if (isDW) {
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B,OpInfo[OpIdx].RegClass,
decodeRs(insn))));
++OpIdx;
}
// Finally add the pointer operand.
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
decodeRn(insn))));
++OpIdx;

6
test/MC/Disassembler/ARM/thumb-tests.txt
View File

@ -154,3 +154,9 @@
# CHECK: ldrd r3, r8, [r11, #-60]
0x5b 0xe9 0x0f 0x38
# CHECK: ldrex r8, [r2]
0x52 0xe8 0x00 0x8f
# CHECK: strexd r1, r7, r8, [r2]
0xc2 0xe8 0x71 0x78