6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-27 02:31:09 +00:00
Code Issues Projects Releases Wiki Activity

[SystemZ] Add sign-extending high-word loads (LBH and LHH)

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191740 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford 2013-10-01 12:11:47 +00:00
parent 55d7d83b6c
commit ced450f0e6
7 changed files with 200 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/SystemZ/SystemZInstrInfo.cpp
View File

@ -806,6 +806,14 @@ SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
splitMove(MI, SystemZ::STD);
return true;
case SystemZ::LBMux:
expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
return true;
case SystemZ::LHMux:
expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
return true;
case SystemZ::LMux:
expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
return true;

16
lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -408,9 +408,21 @@ let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
def : Pat<(sext_inreg GR64:$src, i32),
(LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
// 32-bit extensions from memory.
def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>;
// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH,
// depending on the choice of register.
def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>,
Requires<[FeatureHighWord]>;
def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>;
def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>,
Requires<[FeatureHighWord]>;
// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH,
// depending on the choice of register.
def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>,
Requires<[FeatureHighWord]>;
defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>;
def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>,
Requires<[FeatureHighWord]>;
def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>;
// 64-bit extensions from memory.

48
test/CodeGen/SystemZ/asm-18.ll
View File

@ -50,3 +50,51 @@ define i32 @f2(i32 %old) {
%new = call i32 asm "stepb $1, $2", "=&h,0,h"(i32 %tmp, i32 %tmp)
ret i32 %new
}
; Test sign-extending 8-bit loads into mixtures of high and low registers.
define void @f3(i8 *%ptr1, i8 *%ptr2) {
; CHECK-LABEL: f3:
; CHECK-DAG: lbh [[REG1:%r[0-5]]], 0(%r2)
; CHECK-DAG: lb [[REG2:%r[0-5]]], 0(%r3)
; CHECK-DAG: lbh [[REG3:%r[0-5]]], 4096(%r2)
; CHECK-DAG: lb [[REG4:%r[0-5]]], 524287(%r3)
; CHECK: blah [[REG1]], [[REG2]]
; CHECK: br %r14
%ptr3 = getelementptr i8 *%ptr1, i64 4096
%ptr4 = getelementptr i8 *%ptr2, i64 524287
%val1 = load i8 *%ptr1
%val2 = load i8 *%ptr2
%val3 = load i8 *%ptr3
%val4 = load i8 *%ptr4
%ext1 = sext i8 %val1 to i32
%ext2 = sext i8 %val2 to i32
%ext3 = sext i8 %val3 to i32
%ext4 = sext i8 %val4 to i32
call void asm sideeffect "blah $0, $1, $2, $3",
"h,r,h,r"(i32 %ext1, i32 %ext2, i32 %ext3, i32 %ext4)
ret void
}
; Test sign-extending 16-bit loads into mixtures of high and low registers.
define void @f4(i16 *%ptr1, i16 *%ptr2) {
; CHECK-LABEL: f4:
; CHECK-DAG: lhh [[REG1:%r[0-5]]], 0(%r2)
; CHECK-DAG: lh [[REG2:%r[0-5]]], 0(%r3)
; CHECK-DAG: lhh [[REG3:%r[0-5]]], 4096(%r2)
; CHECK-DAG: lhy [[REG4:%r[0-5]]], 524286(%r3)
; CHECK: blah [[REG1]], [[REG2]]
; CHECK: br %r14
%ptr3 = getelementptr i16 *%ptr1, i64 2048
%ptr4 = getelementptr i16 *%ptr2, i64 262143
%val1 = load i16 *%ptr1
%val2 = load i16 *%ptr2
%val3 = load i16 *%ptr3
%val4 = load i16 *%ptr4
%ext1 = sext i16 %val1 to i32
%ext2 = sext i16 %val2 to i32
%ext3 = sext i16 %val3 to i32
%ext4 = sext i16 %val4 to i32
call void asm sideeffect "blah $0, $1, $2, $3",
"h,r,h,r"(i32 %ext1, i32 %ext2, i32 %ext3, i32 %ext4)
ret void
}

60
test/MC/Disassembler/SystemZ/insns.txt
View File

@ -2461,6 +2461,36 @@
# CHECK: lb %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x76
# CHECK: lbh %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0xc0
# CHECK: lbh %r0, -1
0xe3 0x00 0x0f 0xff 0xff 0xc0
# CHECK: lbh %r0, 0
0xe3 0x00 0x00 0x00 0x00 0xc0
# CHECK: lbh %r0, 1
0xe3 0x00 0x00 0x01 0x00 0xc0
# CHECK: lbh %r0, 524287
0xe3 0x00 0x0f 0xff 0x7f 0xc0
# CHECK: lbh %r0, 0(%r1)
0xe3 0x00 0x10 0x00 0x00 0xc0
# CHECK: lbh %r0, 0(%r15)
0xe3 0x00 0xf0 0x00 0x00 0xc0
# CHECK: lbh %r0, 524287(%r1,%r15)
0xe3 0x01 0xff 0xff 0x7f 0xc0
# CHECK: lbh %r0, 524287(%r15,%r1)
0xe3 0x0f 0x1f 0xff 0x7f 0xc0
# CHECK: lbh %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0xc0
# CHECK: lcdbr %f0, %f9
0xb3 0x13 0x00 0x09
@ -3007,6 +3037,36 @@
# CHECK: lhi %r15, 0
0xa7 0xf8 0x00 0x00
# CHECK: lhh %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0xc4
# CHECK: lhh %r0, -1
0xe3 0x00 0x0f 0xff 0xff 0xc4
# CHECK: lhh %r0, 0
0xe3 0x00 0x00 0x00 0x00 0xc4
# CHECK: lhh %r0, 1
0xe3 0x00 0x00 0x01 0x00 0xc4
# CHECK: lhh %r0, 524287
0xe3 0x00 0x0f 0xff 0x7f 0xc4
# CHECK: lhh %r0, 0(%r1)
0xe3 0x00 0x10 0x00 0x00 0xc4
# CHECK: lhh %r0, 0(%r15)
0xe3 0x00 0xf0 0x00 0x00 0xc4
# CHECK: lhh %r0, 524287(%r1,%r15)
0xe3 0x01 0xff 0xff 0x7f 0xc4
# CHECK: lhh %r0, 524287(%r15,%r1)
0xe3 0x0f 0x1f 0xff 0x7f 0xc4
# CHECK: lhh %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0xc4
# CHECK: lhr %r0, %r15
0xb9 0x27 0x00 0x0f

16
test/MC/SystemZ/insn-bad-z196.s
View File

@ -72,6 +72,14 @@
fixbra %f0, 0, %f2, 0
fixbra %f2, 0, %f0, 0
#CHECK: error: invalid operand
#CHECK: lbh %r0, -524289
#CHECK: error: invalid operand
#CHECK: lbh %r0, 524288
lbh %r0, -524289
lbh %r0, 524288
#CHECK: error: invalid operand
#CHECK: lfh %r0, -524289
#CHECK: error: invalid operand
@ -80,6 +88,14 @@
lfh %r0, -524289
lfh %r0, 524288
#CHECK: error: invalid operand
#CHECK: lhh %r0, -524289
#CHECK: error: invalid operand
#CHECK: lhh %r0, 524288
lhh %r0, -524289
lhh %r0, 524288
#CHECK: error: invalid operand
#CHECK: loc %r0,0,-1
#CHECK: error: invalid operand

10
test/MC/SystemZ/insn-bad.s
View File

@ -1390,6 +1390,11 @@
lb %r0, -524289
lb %r0, 524288
#CHECK: error: {{(instruction requires: high-word)?}}
#CHECK: lbh %r0, 0
lbh %r0, 0
#CHECK: error: invalid register pair
#CHECK: lcxbr %f0, %f2
#CHECK: error: invalid register pair
@ -1560,6 +1565,11 @@
lh %r0, -1
lh %r0, 4096
#CHECK: error: {{(instruction requires: high-word)?}}
#CHECK: lhh %r0, 0
lhh %r0, 0
#CHECK: error: invalid operand
#CHECK: lhi %r0, -32769
#CHECK: error: invalid operand

44
test/MC/SystemZ/insn-good-z196.s
View File

@ -163,6 +163,28 @@
fixbra %f4, 5, %f8, 9
fixbra %f13, 0, %f0, 0
#CHECK: lbh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xc0]
#CHECK: lbh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xc0]
#CHECK: lbh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xc0]
#CHECK: lbh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0xc0]
#CHECK: lbh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0xc0]
#CHECK: lbh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0xc0]
#CHECK: lbh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0xc0]
#CHECK: lbh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0xc0]
#CHECK: lbh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0xc0]
#CHECK: lbh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0xc0]
lbh %r0, -524288
lbh %r0, -1
lbh %r0, 0
lbh %r0, 1
lbh %r0, 524287
lbh %r0, 0(%r1)
lbh %r0, 0(%r15)
lbh %r0, 524287(%r1,%r15)
lbh %r0, 524287(%r15,%r1)
lbh %r15, 0
#CHECK: lfh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xca]
#CHECK: lfh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xca]
#CHECK: lfh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xca]
@ -185,6 +207,28 @@
lfh %r0, 524287(%r15,%r1)
lfh %r15, 0
#CHECK: lhh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xc4]
#CHECK: lhh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xc4]
#CHECK: lhh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xc4]
#CHECK: lhh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0xc4]
#CHECK: lhh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0xc4]
#CHECK: lhh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0xc4]
#CHECK: lhh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0xc4]
#CHECK: lhh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0xc4]
#CHECK: lhh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0xc4]
#CHECK: lhh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0xc4]
lhh %r0, -524288
lhh %r0, -1
lhh %r0, 0
lhh %r0, 1
lhh %r0, 524287
lhh %r0, 0(%r1)
lhh %r0, 0(%r15)
lhh %r0, 524287(%r1,%r15)
lhh %r0, 524287(%r15,%r1)
lhh %r15, 0
#CHECK: loc %r0, 0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0xf2]
#CHECK: loc %r0, 0, 15 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0xf2]
#CHECK: loc %r0, -524288, 0 # encoding: [0xeb,0x00,0x00,0x00,0x80,0xf2]