PHI and INLINEASM are now built-in instructions provided by Target.td

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25674 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/Alpha.td

@@ -38,8 +38,6 @@ include "AlphaRegisterInfo.td"
 include "AlphaInstrInfo.td"
 
 def AlphaInstrInfo : InstrInfo {
-  let PHIInst = PHI;
-
   // Define how we want to layout our target-specific information field.
  // let TSFlagsFields = [];
  // let TSFlagsShifts = [];

lib/Target/Alpha/AlphaInstrInfo.td

@@ -113,8 +113,6 @@ def sub8  : PatFrag<(ops node:$op1, node:$op2),
 
 //Pseudo ops for selection
 
-def PHI : PseudoInstAlpha<(ops variable_ops), "#phi", []>;
-
 def IDEF_I : PseudoInstAlpha<(ops GPRC:$RA), "#idef $RA",
              [(set GPRC:$RA, (undef))]>;
 def IDEF_F32 : PseudoInstAlpha<(ops F4RC:$RA), "#idef $RA",

lib/Target/IA64/IA64.td

@@ -28,9 +28,7 @@ include "IA64RegisterInfo.td"
 
 include "IA64InstrInfo.td"
 
-def IA64InstrInfo : InstrInfo {
+def IA64InstrInfo : InstrInfo { }
-    let PHIInst = PHI;
-}
 
 def IA64 : Target {
   // The following registers are always saved across calls:

lib/Target/IA64/IA64InstrInfo.td

@@ -448,7 +448,6 @@ def : Pat<(i1  0), (CMPNE r0, r0)>; // TODO: any instruction actually *using*
 // TODO: support postincrement (reg, imm9) loads+stores - this needs more
 // tablegen support
 
-def PHI : PseudoInstIA64<(ops variable_ops), "PHI">;
 def IDEF : PseudoInstIA64<(ops variable_ops), "// IDEF">;
 
 def IDEF_GR_D : PseudoInstIA64_DAG<(ops GR:$reg), "// $reg = IDEF",

lib/Target/PowerPC/PPCInstrFormats.td

@@ -644,9 +644,8 @@ class VXRForm_1<bits<10> xo, bit rc, dag OL, string asmstr,
 }
 
 //===----------------------------------------------------------------------===//
-def NoItin : InstrItinClass;
 class Pseudo<dag OL, string asmstr, list<dag> pattern>
-    : I<0, OL, asmstr, NoItin> {
+    : I<0, OL, asmstr, NoItinerary> {
   let PPC64 = 0;
   let VMX = 0;
   let Pattern = pattern;

lib/Target/PowerPC/PPCInstrInfo.td

@@ -194,7 +194,6 @@ def FPContractions : Predicate<"!NoExcessFPPrecision">;
 // PowerPC Instruction Definitions.
 
 // Pseudo-instructions:
-def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
 
 let isLoad = 1, hasCtrlDep = 1 in {
 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
@@ -1087,8 +1086,6 @@ def : Pattern<(xor GPRC:$in, imm:$imm),
 // PowerPCInstrInfo Definition
 //
 def PowerPCInstrInfo : InstrInfo {
-  let PHIInst  = PHI;
-
   let TSFlagsFields = [ "VMX", "PPC64" ];
   let TSFlagsShifts = [ 0, 1 ];
 

lib/Target/Skeleton/Skeleton.td

@@ -21,9 +21,7 @@ include "../Target.td"
 include "SkeletonRegisterInfo.td"
 include "SkeletonInstrInfo.td"
 
-def SkeletonInstrInfo : InstrInfo {
+def SkeletonInstrInfo : InstrInfo { }
-  let PHIInst = PHI;
-}
 
 def Skeleton : Target {
   // Pointers are 32-bits in size.

lib/Target/Skeleton/SkeletonInstrInfo.td

@@ -32,7 +32,6 @@ class SkelInst<string nm, bits<6> opcd, dag ops, Format f> : Instruction {
 }
 
 // Pseudo-instructions:
-def PHI : SkelInst<"PHI", 0, (ops), Pseudo>;          // PHI node...
 def NOP : SkelInst<"NOP", 0, (ops), Pseudo>;          // No-op
 def ADJCALLSTACKDOWN : SkelInst<"ADJCALLSTACKDOWN", 0, (ops), Pseudo>;
 def ADJCALLSTACKUP : SkelInst<"ADJCALLSTACKUP", 0, (ops), Pseudo>;

lib/Target/Sparc/Sparc.td

@@ -43,8 +43,6 @@ include "SparcV8RegisterInfo.td"
 include "SparcV8InstrInfo.td"
 
 def SparcV8InstrInfo : InstrInfo {
-  let PHIInst = PHI;
-
   // Define how we want to layout our target-specific information field.
   let TSFlagsFields = [];
   let TSFlagsShifts = [];

lib/Target/Sparc/SparcInstrInfo.td

@@ -107,7 +107,6 @@ def retflag       : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
 class Pseudo<dag ops, string asmstr, list<dag> pattern>
    : InstV8<ops, asmstr, pattern>;
 
-def PHI : Pseudo<(ops variable_ops), "PHI", []>;
 def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
                                "!ADJCALLSTACKDOWN $amt",
                                [(callseq_start imm:$amt)]>;

lib/Target/SparcV8/SparcV8.td

@@ -43,8 +43,6 @@ include "SparcV8RegisterInfo.td"
 include "SparcV8InstrInfo.td"
 
 def SparcV8InstrInfo : InstrInfo {
-  let PHIInst = PHI;
-
   // Define how we want to layout our target-specific information field.
   let TSFlagsFields = [];
   let TSFlagsShifts = [];

lib/Target/SparcV8/SparcV8InstrInfo.td

@@ -107,7 +107,6 @@ def retflag       : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
 class Pseudo<dag ops, string asmstr, list<dag> pattern>
    : InstV8<ops, asmstr, pattern>;
 
-def PHI : Pseudo<(ops variable_ops), "PHI", []>;
 def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
                                "!ADJCALLSTACKDOWN $amt",
                                [(callseq_start imm:$amt)]>;

lib/Target/SparcV9/SparcV9.td

@@ -31,8 +31,6 @@ include "SparcV9RegisterInfo.td"
 include "SparcV9InstrInfo.td"
 
 def SparcV9InstrInfo : InstrInfo {
-  let PHIInst = PHI;
-
   // Define how we want to layout our TargetSpecific information field.
   let TSFlagsFields = [];
   let TSFlagsShifts = [];

lib/Target/SparcV9/SparcV9InstrInfo.td

@@ -38,9 +38,6 @@ include "SparcV9_F4.td"
 // Instruction list
 //===----------------------------------------------------------------------===//
 
-// Pseudo-instructions
-def PHI     : Pseudo<"phi">;
-
 // Section A.2: Add - p137
 def ADDr    : F3_1<2, 0b000000, "add">;             // add    rs1, rs2, rd
 def ADDi    : F3_2<2, 0b000000, "add">;             // add    rs1, imm, rd

lib/Target/Target.td

@@ -171,7 +171,7 @@ class Instruction {
   bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
   bit noResults    = 0;     // Does this instruction produce no results?
   
-  InstrItinClass Itinerary; // Execution steps used for scheduling. 
+  InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
 }
 
 /// Predicates - These are extra conditionals which are turned into instruction
@@ -213,8 +213,6 @@ def i64imm : Operand<i64>;
 // which are global to the the target machine.
 //
 class InstrInfo {
-  Instruction PHIInst;
-
   // If the target wants to associate some target-specific information with each
   // instruction, it should provide these two lists to indicate how to assemble
   // the target specific information into the 32 bits available.
@@ -229,6 +227,16 @@ class InstrInfo {
   bit isLittleEndianEncoding = 0;
 }
 
+// Standard Instructions.
+def PHI : Instruction {
+  let OperandList = (ops variable_ops);
+  let AsmString = "PHINODE";
+}
+def INLINEASM : Instruction {
+  let OperandList = (ops variable_ops);
+  let AsmString = "";
+}
+
 //===----------------------------------------------------------------------===//
 // AsmWriter - This class can be implemented by targets that need to customize
 // the format of the .s file writer.

lib/Target/X86/X86.td

@@ -98,7 +98,6 @@ include "X86RegisterInfo.td"
 include "X86InstrInfo.td"
 
 def X86InstrInfo : InstrInfo {
-  let PHIInst  = PHI;
 
   // Define how we want to layout our TargetSpecific information field... This
   // should be kept up-to-date with the fields in the X86InstrInfo.h file.

lib/Target/X86/X86InstrInfo.td

@@ -378,9 +378,6 @@ class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
 // Instruction list...
 //
 
-// Pseudo-instructions:
-def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE", []>;        // PHI node.
-
 def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN",
                          [(X86callseq_start imm:$amt)]>;
 def ADJCALLSTACKUP   : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2),