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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-13 10:32:06 +00:00
Clean up Thumb load/store multiple definitions.
There is no non-writeback store multiple instruction in Thumb1, so don't define one. As a result load multiple is the only instantiation of the multiclass, so refactor that away entirely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138338 91177308-0d34-0410-b5e6-96231b3b80d8
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e732cb0043
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lib/Target/ARM
@ -1930,7 +1930,6 @@ ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
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case ARM::STMIB_UPD:
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case ARM::STMIB_UPD:
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case ARM::tLDMIA:
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case ARM::tLDMIA:
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case ARM::tLDMIA_UPD:
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case ARM::tLDMIA_UPD:
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case ARM::tSTMIA:
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case ARM::tSTMIA_UPD:
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case ARM::tSTMIA_UPD:
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case ARM::tPOP_RET:
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case ARM::tPOP_RET:
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case ARM::tPOP:
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case ARM::tPOP:
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@ -2196,7 +2195,6 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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case ARM::STMDA_UPD:
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case ARM::STMDA_UPD:
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case ARM::STMDB_UPD:
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case ARM::STMDB_UPD:
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case ARM::STMIB_UPD:
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case ARM::STMIB_UPD:
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case ARM::tSTMIA:
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case ARM::tSTMIA_UPD:
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case ARM::tSTMIA_UPD:
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case ARM::tPOP_RET:
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case ARM::tPOP_RET:
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case ARM::tPOP:
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case ARM::tPOP:
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@ -694,24 +694,25 @@ def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
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// Load / store multiple Instructions.
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// Load / store multiple Instructions.
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//
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//
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multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
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// These require base address to be written back or one of the loaded regs.
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InstrItinClass itin_upd, bits<6> T1Enc,
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let neverHasSideEffects = 1 in {
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bit L_bit, string baseOpc> {
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def IA :
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
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T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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itin, !strconcat(asm, "${p}\t$Rn, $regs"), []>,
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IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
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T1Encoding<T1Enc> {
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bits<3> Rn;
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bits<3> Rn;
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bits<8> regs;
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bits<8> regs;
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let Inst{10-8} = Rn;
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let Inst{10-8} = Rn;
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let Inst{7-0} = regs;
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let Inst{7-0} = regs;
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}
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}
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def IA_UPD :
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// Writeback version is just a pseudo, as there's no encoding difference.
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// Writeback happens iff the base register is not in the destination register
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// list.
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def tLDMIA_UPD :
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InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
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InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
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"$Rn = $wb", itin_upd>,
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"$Rn = $wb", IIC_iLoad_mu>,
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PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA"))
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PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
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tGPR:$Rn, pred:$p, reglist:$regs)> {
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let Size = 2;
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let Size = 2;
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let OutOperandList = (outs GPR:$wb);
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let OutOperandList = (outs GPR:$wb);
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let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
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let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
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@ -719,19 +720,19 @@ multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
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let isCodeGenOnly = 1;
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let isCodeGenOnly = 1;
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let isPseudo = 1;
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let isPseudo = 1;
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list<Predicate> Predicates = [IsThumb];
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list<Predicate> Predicates = [IsThumb];
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}
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}
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}
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// These require base address to be written back or one of the loaded regs.
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// There is no non-writeback version of STM for Thumb.
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let neverHasSideEffects = 1 in {
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
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defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
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{1,1,0,0,1,?}, 1, "tLDM">;
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
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defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
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def tSTMIA_UPD : T1I<(outs),
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{1,1,0,0,0,?}, 0, "tSTM">;
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(ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IIC_iStore_mu, "stm${p}\t$Rn!, $regs", []>,
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T1Encoding<{1,1,0,0,0,?}> {
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bits<3> Rn;
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bits<8> regs;
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let Inst{10-8} = Rn;
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let Inst{7-0} = regs;
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}
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} // neverHasSideEffects
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} // neverHasSideEffects
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@ -739,7 +740,6 @@ def : InstAlias<"ldm${p} $Rn!, $regs",
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(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
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(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
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Requires<[IsThumb, IsThumb1Only]>;
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Requires<[IsThumb, IsThumb1Only]>;
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let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
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let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
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def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
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def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
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IIC_iPop,
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IIC_iPop,
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@ -1147,8 +1147,6 @@ def tSUBrr : // A8.6.212
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"sub", "\t$Rd, $Rn, $Rm",
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"sub", "\t$Rd, $Rn, $Rm",
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[(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
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[(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
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// TODO: A7-96: STMIA - store multiple.
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// Sign-extend byte
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// Sign-extend byte
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def tSXTB : // A8.6.222
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def tSXTB : // A8.6.222
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T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
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T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
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@ -146,7 +146,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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return;
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return;
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}
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}
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if (Opcode == ARM::tLDMIA || Opcode == ARM::tSTMIA) {
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if (Opcode == ARM::tLDMIA) {
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bool Writeback = true;
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bool Writeback = true;
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unsigned BaseReg = MI->getOperand(0).getReg();
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unsigned BaseReg = MI->getOperand(0).getReg();
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for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
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for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
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@ -154,12 +154,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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Writeback = false;
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Writeback = false;
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}
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}
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if (Opcode == ARM::tLDMIA)
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O << "\tldm";
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O << "\tldm";
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else if (Opcode == ARM::tSTMIA)
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O << "\tstm";
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else
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llvm_unreachable("Unknown opcode!");
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printPredicateOperand(MI, 1, O);
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printPredicateOperand(MI, 1, O);
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O << '\t' << getRegisterName(BaseReg);
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O << '\t' << getRegisterName(BaseReg);
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