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Improvements to tail call code. No functional effect
unless using -arm-tail-calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105515 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1259,22 +1259,8 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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Ops.push_back(InFlag);
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
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if (isTailCall) {
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// If this is the first return lowered for this function, add the regs
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// to the liveout set for the function.
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if (MF.getRegInfo().liveout_empty()) {
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
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*DAG.getContext());
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CCInfo.AnalyzeCallResult(Ins,
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CCAssignFnForNode(CallConv, /* Return*/ true,
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isVarArg));
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for (unsigned i = 0; i != RVLocs.size(); ++i)
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if (RVLocs[i].isRegLoc())
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MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
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}
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if (isTailCall)
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return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
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}
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// Returns a chain and a flag for retval copy to use.
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Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
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@ -1354,7 +1340,6 @@ ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SelectionDAG& DAG) const {
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// const MachineFunction &MF = DAG.getMachineFunction();
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const Function *CallerF = DAG.getMachineFunction().getFunction();
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CallingConv::ID CallerCC = CallerF->getCallingConv();
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bool CCMatch = CallerCC == CalleeCC;
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@ -1427,14 +1412,31 @@ ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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const MachineRegisterInfo *MRI = &MF.getRegInfo();
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const ARMInstrInfo *TII =
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((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
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i != e;
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++i, ++realArgIdx) {
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CCValAssign &VA = ArgLocs[i];
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EVT RegVT = VA.getLocVT();
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SDValue Arg = Outs[i].Val;
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ISD::ArgFlagsTy Flags = Outs[i].Flags;
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SDValue Arg = Outs[realArgIdx].Val;
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ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
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if (VA.getLocInfo() == CCValAssign::Indirect)
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return false;
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if (!VA.isRegLoc()) {
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if (VA.needsCustom()) {
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// f64 and vector types are split into multiple registers or
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// register/stack-slot combinations. The types will not match
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// the registers; give up on memory f64 refs until we figure
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// out what to do about this.
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if (!VA.isRegLoc())
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return false;
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if (!ArgLocs[++i].isRegLoc())
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return false;
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if (RegVT == MVT::v2f64) {
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if (!ArgLocs[++i].isRegLoc())
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return false;
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if (!ArgLocs[++i].isRegLoc())
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return false;
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}
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} else if (!VA.isRegLoc()) {
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if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
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MFI, MRI, TII))
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return false;
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