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https://github.com/c64scene-ar/llvm-6502.git
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Make conversions of i8/i16 to ppcf128 work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48493 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -6713,6 +6713,19 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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case ISD::UINT_TO_FP: {
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case ISD::UINT_TO_FP: {
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bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
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bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
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MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
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MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
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// Promote the operand if needed. Do this before checking for
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// ppcf128 so conversions of i16 and i8 work.
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if (getTypeAction(SrcVT) == Promote) {
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SDOperand Tmp = PromoteOp(Node->getOperand(0));
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Tmp = isSigned
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? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
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DAG.getValueType(SrcVT))
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: DAG.getZeroExtendInReg(Tmp, SrcVT);
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Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
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SrcVT = Node->getOperand(0).getValueType();
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}
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if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
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if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
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static const uint64_t zero = 0;
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static const uint64_t zero = 0;
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if (isSigned) {
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if (isSigned) {
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@@ -6757,16 +6770,6 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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break;
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break;
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}
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}
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// Promote the operand if needed.
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if (getTypeAction(SrcVT) == Promote) {
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SDOperand Tmp = PromoteOp(Node->getOperand(0));
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Tmp = isSigned
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? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
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DAG.getValueType(SrcVT))
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: DAG.getZeroExtendInReg(Tmp, SrcVT);
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Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
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}
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Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
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Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
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Node->getOperand(0));
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Node->getOperand(0));
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ExpandOp(Lo, Lo, Hi);
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ExpandOp(Lo, Lo, Hi);
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32
test/CodeGen/PowerPC/ppcf128-3.ll
Normal file
32
test/CodeGen/PowerPC/ppcf128-3.ll
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@@ -0,0 +1,32 @@
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; RUN: llvm-as < %s | llc -march=ppc32
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%struct.stp_sequence = type { double, double }
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define i32 @stp_sequence_set_short_data(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
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entry:
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%tmp1112 = sitofp i16 0 to ppc_fp128 ; <ppc_fp128> [#uses=1]
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%tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0]
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ret i32 0
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}
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define i32 @stp_sequence_set_short_data2(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
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entry:
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%tmp1112 = sitofp i8 0 to ppc_fp128 ; <ppc_fp128> [#uses=1]
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%tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0]
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ret i32 0
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}
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define i32 @stp_sequence_set_short_data3(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
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entry:
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%tmp1112 = uitofp i16 0 to ppc_fp128 ; <ppc_fp128> [#uses=1]
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%tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0]
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ret i32 0
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}
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define i32 @stp_sequence_set_short_data4(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
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entry:
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%tmp1112 = uitofp i8 0 to ppc_fp128 ; <ppc_fp128> [#uses=1]
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%tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0]
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ret i32 0
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}
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declare i32 @__inline_isfinite(...)
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