mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-06 06:33:24 +00:00
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117997 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
parent
4053e63a4b
commit
cf667be17b
@ -102,6 +102,7 @@ namespace {
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unsigned getMachineSoImmOpValue(unsigned SoImm);
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unsigned getAddrMode6RegisterOperand(const MachineInstr &MI);
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unsigned getAddrMode6OffsetOperand(const MachineInstr &MI);
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unsigned getAddrModeSBit(const MachineInstr &MI,
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const TargetInstrDesc &TID) const;
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@ -175,6 +176,8 @@ namespace {
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const { return 0; }
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unsigned getAddrMode6RegisterOperand(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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unsigned getAddrMode6OffsetOperand(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
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unsigned Op) const { return 0; }
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unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
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@ -478,6 +478,7 @@ def addrmode6 : Operand<i32>,
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def am6offset : Operand<i32> {
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let PrintMethod = "printAddrMode6OffsetOperand";
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let MIOperandInfo = (ops GPR);
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string EncoderMethod = "getAddrMode6OffsetOperand";
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}
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// addrmodepc := pc + reg
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@ -284,22 +284,28 @@ def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
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// VLD2 : Vector Load (multiple 2-element structures)
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class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
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: NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
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(ins addrmode6:$addr), IIC_VLD2,
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"vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
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: NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
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(ins addrmode6:$Rn), IIC_VLD2,
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"vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
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let Rm = 0b1111;
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let Inst{5-4} = Rn{5-4};
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}
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class VLD2Q<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b10, 0b0011, op7_4,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$addr), IIC_VLD2x2,
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"vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
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(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$Rn), IIC_VLD2x2,
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"vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
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let Rm = 0b1111;
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let Inst{5-4} = Rn{5-4};
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}
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def VLD2d8 : VLD2D<0b1000, 0b0000, "8">;
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def VLD2d16 : VLD2D<0b1000, 0b0100, "16">;
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def VLD2d32 : VLD2D<0b1000, 0b1000, "32">;
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def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
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def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
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def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
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def VLD2q8 : VLD2Q<0b0000, "8">;
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def VLD2q16 : VLD2Q<0b0100, "16">;
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def VLD2q32 : VLD2Q<0b1000, "32">;
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def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
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def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
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def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
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def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
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def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
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@ -311,24 +317,28 @@ def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
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// ...with address register writeback:
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class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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: NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD2u,
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"vld2", Dt, "\\{$dst1, $dst2\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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: NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
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(ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
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"vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
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"$Rn.addr = $wb", []> {
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let Inst{5-4} = Rn{5-4};
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}
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class VLD2QWB<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b10, 0b0011, op7_4,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD2x2u,
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"vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
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(ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
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"vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
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"$Rn.addr = $wb", []> {
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let Inst{5-4} = Rn{5-4};
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}
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def VLD2d8_UPD : VLD2DWB<0b1000, 0b0000, "8">;
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def VLD2d16_UPD : VLD2DWB<0b1000, 0b0100, "16">;
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def VLD2d32_UPD : VLD2DWB<0b1000, 0b1000, "32">;
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def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
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def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
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def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
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def VLD2q8_UPD : VLD2QWB<0b0000, "8">;
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def VLD2q16_UPD : VLD2QWB<0b0100, "16">;
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def VLD2q32_UPD : VLD2QWB<0b1000, "32">;
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def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
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def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
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def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
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def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
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def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
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@ -339,22 +349,25 @@ def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
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def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
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// ...with double-spaced registers (for disassembly only):
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def VLD2b8 : VLD2D<0b1001, 0b0000, "8">;
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def VLD2b16 : VLD2D<0b1001, 0b0100, "16">;
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def VLD2b32 : VLD2D<0b1001, 0b1000, "32">;
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def VLD2b8_UPD : VLD2DWB<0b1001, 0b0000, "8">;
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def VLD2b16_UPD : VLD2DWB<0b1001, 0b0100, "16">;
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def VLD2b32_UPD : VLD2DWB<0b1001, 0b1000, "32">;
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def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
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def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
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def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
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def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
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def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
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def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
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// VLD3 : Vector Load (multiple 3-element structures)
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class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
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: NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
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(ins addrmode6:$addr), IIC_VLD3,
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"vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
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: NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
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(ins addrmode6:$Rn), IIC_VLD3,
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"vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
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let Rm = 0b1111;
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let Inst{4} = Rn{4};
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}
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def VLD3d8 : VLD3D<0b0100, 0b0000, "8">;
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def VLD3d16 : VLD3D<0b0100, 0b0100, "16">;
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def VLD3d32 : VLD3D<0b0100, 0b1000, "32">;
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def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
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def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
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def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
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def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
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def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
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@ -363,26 +376,28 @@ def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
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// ...with address register writeback:
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class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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: NLdSt<0, 0b10, op11_8, op7_4,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD3u,
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"vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
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(ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
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"vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
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"$Rn.addr = $wb", []> {
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let Inst{4} = Rn{4};
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}
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def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">;
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def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
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def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
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def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
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def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
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def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
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def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
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def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
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def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
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// ...with double-spaced registers (non-updating versions for disassembly only):
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def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
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def VLD3q16 : VLD3D<0b0101, 0b0100, "16">;
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def VLD3q32 : VLD3D<0b0101, 0b1000, "32">;
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def VLD3q8_UPD : VLD3DWB<0b0101, 0b0000, "8">;
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def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">;
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def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">;
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def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
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def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
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def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
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def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
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def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
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def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
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def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
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def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
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@ -396,13 +411,16 @@ def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
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// VLD4 : Vector Load (multiple 4-element structures)
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class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
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: NLdSt<0, 0b10, op11_8, op7_4,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$addr), IIC_VLD4,
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"vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
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(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$Rn), IIC_VLD4,
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"vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
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let Rm = 0b1111;
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let Inst{5-4} = Rn{5-4};
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}
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def VLD4d8 : VLD4D<0b0000, 0b0000, "8">;
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def VLD4d16 : VLD4D<0b0000, 0b0100, "16">;
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def VLD4d32 : VLD4D<0b0000, 0b1000, "32">;
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def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
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def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
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def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
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def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
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def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
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@ -411,26 +429,28 @@ def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
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// ...with address register writeback:
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class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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: NLdSt<0, 0b10, op11_8, op7_4,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD4,
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"vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
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(ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4,
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"vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
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"$Rn.addr = $wb", []> {
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let Inst{5-4} = Rn{5-4};
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}
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def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">;
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def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
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def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
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def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
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def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
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def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
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def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
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def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
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def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
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// ...with double-spaced registers (non-updating versions for disassembly only):
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def VLD4q8 : VLD4D<0b0001, 0b0000, "8">;
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def VLD4q16 : VLD4D<0b0001, 0b0100, "16">;
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def VLD4q32 : VLD4D<0b0001, 0b1000, "32">;
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def VLD4q8_UPD : VLD4DWB<0b0001, 0b0000, "8">;
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def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">;
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def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">;
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def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
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def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
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def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
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def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
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def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
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def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
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def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
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def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
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@ -100,6 +100,7 @@ public:
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unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const;
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unsigned getAddrMode6RegisterOperand(const MCInst &MI, unsigned Op) const;
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unsigned getAddrMode6OffsetOperand(const MCInst &MI, unsigned Op) const;
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unsigned getNumFixupKinds() const {
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assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
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@ -312,6 +313,14 @@ unsigned ARMMCCodeEmitter::getAddrMode6RegisterOperand(const MCInst &MI,
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return RegNo | (Align << 4);
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}
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unsigned ARMMCCodeEmitter::getAddrMode6OffsetOperand(const MCInst &MI,
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unsigned Op) const {
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const MCOperand ®no = MI.getOperand(Op);
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if (regno.getReg() == 0) return 0x0D;
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return regno.getReg();
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}
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void ARMMCCodeEmitter::
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EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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@ -17,3 +17,57 @@
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vld1.32 {d16, d17}, [r0]
|
||||
@ CHECK: vld1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x60,0xf4]
|
||||
vld1.64 {d16, d17}, [r0]
|
||||
|
||||
@ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf4]
|
||||
vld2.8 {d16, d17}, [r0, :64]
|
||||
@ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf4]
|
||||
vld2.16 {d16, d17}, [r0, :128]
|
||||
@ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x60,0xf4]
|
||||
vld2.32 {d16, d17}, [r0]
|
||||
@ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x60,0xf4]
|
||||
vld2.8 {d16, d17, d18, d19}, [r0, :64]
|
||||
@ CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf4]
|
||||
vld2.16 {d16, d17, d18, d19}, [r0, :128]
|
||||
@ CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf4]
|
||||
vld2.32 {d16, d17, d18, d19}, [r0, :256]
|
||||
|
||||
@ CHECK: vld3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x60,0xf4]
|
||||
vld3.8 {d16, d17, d18}, [r0, :64]
|
||||
@ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x60,0xf4]
|
||||
vld3.16 {d16, d17, d18}, [r0]
|
||||
@ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x60,0xf4]
|
||||
vld3.32 {d16, d17, d18}, [r0]
|
||||
@ CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x60,0xf4]
|
||||
vld3.8 {d16, d18, d20}, [r0, :64]!
|
||||
@ CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x60,0xf4]
|
||||
vld3.8 {d17, d19, d21}, [r0, :64]!
|
||||
@ CHECK: vld3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x60,0xf4]
|
||||
vld3.16 {d16, d18, d20}, [r0]!
|
||||
@ CHECK: vld3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x60,0xf4]
|
||||
vld3.16 {d17, d19, d21}, [r0]!
|
||||
@ CHECK: vld3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x60,0xf4]
|
||||
vld3.32 {d16, d18, d20}, [r0]!
|
||||
@ CHECK: vld3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x60,0xf4]
|
||||
vld3.32 {d17, d19, d21}, [r0]!
|
||||
|
||||
@ CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x60,0xf4]
|
||||
vld4.8 {d16, d17, d18, d19}, [r0, :64]
|
||||
@ CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x60,0xf4]
|
||||
vld4.16 {d16, d17, d18, d19}, [r0, :128]
|
||||
@ CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x00,0x60,0xf4]
|
||||
vld4.32 {d16, d17, d18, d19}, [r0, :256]
|
||||
@ CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x60,0xf4]
|
||||
vld4.8 {d16, d18, d20, d22}, [r0, :256]!
|
||||
@ CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x60,0xf4]
|
||||
vld4.8 {d17, d19, d21, d23}, [r0, :256]!
|
||||
@ CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x60,0xf4]
|
||||
vld4.16 {d16, d18, d20, d22}, [r0]!
|
||||
@ CHECK: vld4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x60,0xf4]
|
||||
vld4.16 {d17, d19, d21, d23}, [r0]!
|
||||
@ CHECK: vld4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x60,0xf4]
|
||||
vld4.32 {d16, d18, d20, d22}, [r0]!
|
||||
@ CHECK: vld4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x60,0xf4]
|
||||
vld4.32 {d17, d19, d21, d23}, [r0]!
|
||||
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user