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simplify call code, remove pseudo ops for div and rem, track more loads and stores

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22322 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
2005-07-01 19:12:13 +00:00
parent 5de8b9d796
commit cf8bf388ea
3 changed files with 92 additions and 80 deletions
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16
lib/Target/Alpha/AlphaRegisterInfo.cpp
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@@ -31,6 +31,10 @@
#include <iostream>
using namespace llvm;
namespace llvm {
extern cl::opt<bool> EnableAlphaLSMark;
}
//These describe LDAx
static const int IMM_LOW = -32768;
static const int IMM_HIGH = 32767;
@@ -50,6 +54,12 @@ static long getLower16(long l)
return l - h * IMM_MULT;
}
static int getUID()
{
static int id = 0;
return ++id;
}
AlphaRegisterInfo::AlphaRegisterInfo()
: AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP)
{
@@ -68,6 +78,9 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
unsigned SrcReg, int FrameIdx) const {
//std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
if (EnableAlphaLSMark)
BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(1)
.addImm(getUID());
if (getClass(SrcReg) == Alpha::FPRCRegisterClass)
BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (getClass(SrcReg) == Alpha::GPRCRegisterClass)
@@ -81,6 +94,9 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx) const{
//std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
if (EnableAlphaLSMark)
BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2)
.addImm(getUID());
if (getClass(DestReg) == Alpha::FPRCRegisterClass)
BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (getClass(DestReg) == Alpha::GPRCRegisterClass)