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PR13578: Teach MachineCSE that instructions that use a constant register can be CSE'd safely.

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This is common e.g. when doing rip-relative addressing on x86_64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161728 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2012-08-11 19:05:13 +00:00
parent f4cfc4423c
commit cfc0ad6e48
3 changed files with 29 additions and 4 deletions
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7
lib/CodeGen/MachineCSE.cpp
View File

@ -215,8 +215,11 @@ bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
if (MO.isDef() && if (MO.isDef() &&
(MO.isDead() || isPhysDefTriviallyDead(Reg, I, MBB->end()))) (MO.isDead() || isPhysDefTriviallyDead(Reg, I, MBB->end())))
continue; continue;
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
PhysRefs.insert(*AI); // Reading constant physregs is ok.
if (!MRI->isConstantPhysReg(*AI, *MBB->getParent()))
PhysRefs.insert(*AI);
}
if (MO.isDef()) if (MO.isDef())
PhysDefs.push_back(Reg); PhysDefs.push_back(Reg);
} }

4
test/CodeGen/X86/lsr-loop-exit-cond.ll
View File

@ -3,11 +3,11 @@
; CHECK: t: ; CHECK: t:
; CHECK: decq ; CHECK: decq
; CHECK-NEXT: movl (%r11,%rax,4), %eax ; CHECK-NEXT: movl (%r9,%rax,4), %eax
; CHECK-NEXT: jne ; CHECK-NEXT: jne
; ATOM: t: ; ATOM: t:
; ATOM: movl (%r10,%rax,4), %eax ; ATOM: movl (%r9,%rax,4), %eax
; ATOM-NEXT: decq ; ATOM-NEXT: decq
; ATOM-NEXT: jne ; ATOM-NEXT: jne

22
test/CodeGen/X86/machine-cse.ll
View File

@ -134,3 +134,25 @@ return:
%retval.0 = phi i8* [ null, %entry ], [ null, %do.cond ], [ %p.0, %do.body ] %retval.0 = phi i8* [ null, %entry ], [ null, %do.cond ], [ %p.0, %do.body ]
ret i8* %retval.0 ret i8* %retval.0
} }
; PR13578
@t2_global = external global i32
declare i1 @t2_func()
define i32 @t2() {
store i32 42, i32* @t2_global
%c = call i1 @t2_func()
br i1 %c, label %a, label %b
a:
%l = load i32* @t2_global
ret i32 %l
b:
ret i32 0
; CHECK: t2:
; CHECK: t2_global@GOTPCREL(%rip)
; CHECK-NOT: t2_global@GOTPCREL(%rip)
}