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Fix an abort in instcombine when folding creates a vector rem instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43743 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2007-11-05 23:16:33 +00:00
parent f1ba1cad38
commit cff550995b
2 changed files with 18 additions and 5 deletions
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6
lib/Transforms/Scalar/InstructionCombining.cpp
View File

@ -2622,6 +2622,7 @@ Instruction *InstCombiner::visitSDiv(BinaryOperator &I) {
if (I.getType()->isInteger()) { if (I.getType()->isInteger()) {
APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits())); APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits()));
if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) { if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) {
// X sdiv Y -> X udiv Y, iff X and Y don't have sign bit set
return BinaryOperator::createUDiv(Op0, Op1, I.getName()); return BinaryOperator::createUDiv(Op0, Op1, I.getName());
} }
} }
@ -2811,6 +2812,7 @@ Instruction *InstCombiner::visitURem(BinaryOperator &I) {
Instruction *InstCombiner::visitSRem(BinaryOperator &I) { Instruction *InstCombiner::visitSRem(BinaryOperator &I) {
Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
// Handle the integer rem common cases
if (Instruction *common = commonIRemTransforms(I)) if (Instruction *common = commonIRemTransforms(I))
return common; return common;
@ -2823,13 +2825,15 @@ Instruction *InstCombiner::visitSRem(BinaryOperator &I) {
return &I; return &I;
} }
// If the top bits of both operands are zero (i.e. we can prove they are // If the sign bits of both operands are zero (i.e. we can prove they are
// unsigned inputs), turn this into a urem. // unsigned inputs), turn this into a urem.
if (I.getType()->isInteger()) {
APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits())); APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits()));
if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) { if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) {
// X srem Y -> X urem Y, iff X and Y don't have sign bit set // X srem Y -> X urem Y, iff X and Y don't have sign bit set
return BinaryOperator::createURem(Op0, Op1, I.getName()); return BinaryOperator::createURem(Op0, Op1, I.getName());
} }
}
return 0; return 0;
} }

9
test/Transforms/InstCombine/vector-srem.ll Normal file
View File

@ -0,0 +1,9 @@
; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep {srem <4 x i32>}
define <4 x i32> @foo(<4 x i32> %t, <4 x i32> %u)
{
%k = sdiv <4 x i32> %t, %u
%l = mul <4 x i32> %k, %u
%m = sub <4 x i32> %t, %l
ret <4 x i32> %m
}