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Fix test-llvm failures.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128906 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-05 18:41:40 +00:00
parent a41af7aeef
commit d05a824e1a
6 changed files with 13 additions and 13 deletions
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10
test/CodeGen/ARM/constants.ll
View File

@ -14,31 +14,31 @@ define i32 @f2() {
define i32 @f3() {
; CHECK: f3
; CHECK: mov r0, #1, 24
; CHECK: mov r0, #1, #24
ret i32 256
}
define i32 @f4() {
; CHECK: f4
; CHECK: orr{{.*}}#1, 24
; CHECK: orr{{.*}}#1, #24
ret i32 257
}
define i32 @f5() {
; CHECK: f5
; CHECK: mov r0, #255, 2
; CHECK: mov r0, #255, #2
ret i32 -1073741761
}
define i32 @f6() {
; CHECK: f6
; CHECK: mov r0, #63, 28
; CHECK: mov r0, #63, #28
ret i32 1008
}
define void @f7(i32 %a) {
; CHECK: f7
; CHECK: cmp r0, #1, 16
; CHECK: cmp r0, #1, #16
%b = icmp ugt i32 %a, 65536
br i1 %b, label %r, label %r
r:

2
test/CodeGen/ARM/fp.ll
View File

@ -51,7 +51,7 @@ entry:
define float @h2() {
;CHECK: h2:
;CHECK: mov r0, #254, 10
;CHECK: mov r0, #254, #10
entry:
ret float 1.000000e+00
}

6
test/CodeGen/ARM/long.ll
View File

@ -14,14 +14,14 @@ entry:
define i64 @f3() {
; CHECK: f3:
; CHECK: mvn r0, #2, 2
; CHECK: mvn r0, #2, #2
entry:
ret i64 2147483647
}
define i64 @f4() {
; CHECK: f4:
; CHECK: mov r0, #2, 2
; CHECK: mov r0, #2, #2
entry:
ret i64 2147483648
}
@ -29,7 +29,7 @@ entry:
define i64 @f5() {
; CHECK: f5:
; CHECK: mvn r0, #0
; CHECK: mvn r1, #2, 2
; CHECK: mvn r1, #2, #2
entry:
ret i64 9223372036854775807
}

4
test/CodeGen/ARM/select-imm.ll
View File

@ -6,7 +6,7 @@ define i32 @t1(i32 %c) nounwind readnone {
entry:
; ARM: t1:
; ARM: mov r1, #101
; ARM: orr r1, r1, #1, 24
; ARM: orr r1, r1, #1, #24
; ARM: movgt r0, #123
; ARMT2: t1:
@ -27,7 +27,7 @@ entry:
; ARM: t2:
; ARM: mov r0, #123
; ARM: movgt r0, #101
; ARM: orrgt r0, r0, #1, 24
; ARM: orrgt r0, r0, #1, #24
; ARMT2: t2:
; ARMT2: mov r0, #123

2
test/CodeGen/ARM/select_xform.ll
View File

@ -4,7 +4,7 @@
define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
; ARM: t1:
; ARM: sub r0, r1, #6, 2
; ARM: sub r0, r1, #6, #2
; ARM: movgt r0, r1
; T2: t1:

2
test/CodeGen/ARM/sub.ll
View File

@ -12,7 +12,7 @@ define i64 @f1(i64 %a) {
; 66846720 = 0x03fc0000
define i64 @f2(i64 %a) {
; CHECK: f2
; CHECK: subs r0, r0, #255, 14
; CHECK: subs r0, r0, #255, #14
; CHECK: sbc r1, r1, #0
%tmp = sub i64 %a, 66846720
ret i64 %tmp