[AArch64] Overload NEON signed/unsigned integer convert to floating-point

LLVM AArch64 intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196962 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/IR/IntrinsicsAArch64.td

@@ -229,16 +229,12 @@ def int_aarch64_neon_vpfminnm :
   Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
 
 // Scalar Signed Integer Convert To Floating-point
-def int_aarch64_neon_vcvtf32_s32 :
+def int_aarch64_neon_vcvtint2fps :
-  Intrinsic<[llvm_float_ty], [llvm_v1i32_ty], [IntrNoMem]>;
+  Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
-def int_aarch64_neon_vcvtf64_s64 :
-  Intrinsic<[llvm_double_ty], [llvm_v1i64_ty], [IntrNoMem]>;
 
 // Scalar Unsigned Integer Convert To Floating-point
-def int_aarch64_neon_vcvtf32_u32 :
+def int_aarch64_neon_vcvtint2fpu :
-  Intrinsic<[llvm_float_ty], [llvm_v1i32_ty], [IntrNoMem]>;
+  Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
-def int_aarch64_neon_vcvtf64_u64 :
-  Intrinsic<[llvm_double_ty], [llvm_v1i64_ty], [IntrNoMem]>;
 
 // Scalar Floating-point Convert
 def int_aarch64_neon_fcvtxn :

lib/Target/AArch64/AArch64InstrNEON.td

@@ -4324,13 +4324,12 @@ class Neon_Scalar2SameMisc_vcvt_D_size_patterns<SDPatternOperator opnode,
   : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))),
             (INSTD FPR64:$Rn)>;
 
-multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator Sopnode,
+multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator opnode,
-                                                     SDPatternOperator Dopnode,
                                                      Instruction INSTS,
                                                      Instruction INSTD> {
-  def : Pat<(f32 (Sopnode (v1i32 FPR32:$Rn))),
+  def : Pat<(f32 (opnode (v1i32 FPR32:$Rn))),
             (INSTS FPR32:$Rn)>;
-  def : Pat<(f64 (Dopnode (v1i64 FPR64:$Rn))),
+  def : Pat<(f64 (opnode (v1i64 FPR64:$Rn))),
             (INSTD FPR64:$Rn)>;
 }
 
@@ -4971,14 +4970,12 @@ defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
 
 // Scalar Signed Integer Convert To Floating-point
 defm SCVTF  : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
-defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_s32,
+defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fps,
-                                                 int_aarch64_neon_vcvtf64_s64,
                                                  SCVTFss, SCVTFdd>;
 
 // Scalar Unsigned Integer Convert To Floating-point
 defm UCVTF  : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
-defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_u32,
+defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fpu,
-                                                 int_aarch64_neon_vcvtf64_u64,
                                                  UCVTFss, UCVTFdd>;
 
 // Scalar Floating-point Converts

test/CodeGen/AArch64/neon-scalar-cvt.ll

@@ -5,44 +5,44 @@ define float @test_vcvts_f32_s32(i32 %a) {
 ; CHECK: scvtf {{s[0-9]+}}, {{s[0-9]+}}
 entry:
   %vcvtf.i = insertelement <1 x i32> undef, i32 %a, i32 0
-  %0 = call float @llvm.aarch64.neon.vcvtf32.s32(<1 x i32> %vcvtf.i)
+  %0 = call float @llvm.aarch64.neon.vcvtint2fps.f32.v1i32(<1 x i32> %vcvtf.i)
   ret float %0
 }
 
-declare float @llvm.aarch64.neon.vcvtf32.s32(<1 x i32>)
+declare float @llvm.aarch64.neon.vcvtint2fps.f32.v1i32(<1 x i32>)
 
 define double @test_vcvtd_f64_s64(i64 %a) {
 ; CHECK: test_vcvtd_f64_s64
 ; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
 entry:
   %vcvtf.i = insertelement <1 x i64> undef, i64 %a, i32 0
-  %0 = call double @llvm.aarch64.neon.vcvtf64.s64(<1 x i64> %vcvtf.i)
+  %0 = call double @llvm.aarch64.neon.vcvtint2fps.f64.v1i64(<1 x i64> %vcvtf.i)
   ret double %0
 }
 
-declare double @llvm.aarch64.neon.vcvtf64.s64(<1 x i64>)
+declare double @llvm.aarch64.neon.vcvtint2fps.f64.v1i64(<1 x i64>)
 
 define float @test_vcvts_f32_u32(i32 %a) {
 ; CHECK: test_vcvts_f32_u32
 ; CHECK: ucvtf {{s[0-9]+}}, {{s[0-9]+}}
 entry:
   %vcvtf.i = insertelement <1 x i32> undef, i32 %a, i32 0
-  %0 = call float @llvm.aarch64.neon.vcvtf32.u32(<1 x i32> %vcvtf.i)
+  %0 = call float @llvm.aarch64.neon.vcvtint2fpu.f32.v1i32(<1 x i32> %vcvtf.i)
   ret float %0
 }
 
-declare float @llvm.aarch64.neon.vcvtf32.u32(<1 x i32>)
+declare float @llvm.aarch64.neon.vcvtint2fpu.f32.v1i32(<1 x i32>)
 
 define double @test_vcvtd_f64_u64(i64 %a) {
 ; CHECK: test_vcvtd_f64_u64
 ; CHECK: ucvtf {{d[0-9]+}}, {{d[0-9]+}}
 entry:
   %vcvtf.i = insertelement <1 x i64> undef, i64 %a, i32 0
-  %0 = call double @llvm.aarch64.neon.vcvtf64.u64(<1 x i64> %vcvtf.i)
+  %0 = call double @llvm.aarch64.neon.vcvtint2fpu.f64.v1i64(<1 x i64> %vcvtf.i)
   ret double %0
 }
 
-declare double @llvm.aarch64.neon.vcvtf64.u64(<1 x i64>)
+declare double @llvm.aarch64.neon.vcvtint2fpu.f64.v1i64(<1 x i64>)
 
 define float @test_vcvts_n_f32_s32(i32 %a) {
 ; CHECK: test_vcvts_n_f32_s32