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Mark flag neverHasSideEffects of pattern-less instructions that do not have

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any side effects.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153551 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-03-28 00:21:37 +00:00
parent da942482a3
commit d0b5c65b16
1 changed files with 5 additions and 0 deletions
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5
lib/Target/Mips/MipsInstrInfo.td
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@ -365,6 +365,7 @@ class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
FI<op, (outs RC:$rt), (ins Imm:$imm16),
!strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
let rs = 0;
let neverHasSideEffects = 1;
}
class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
@ -555,6 +556,7 @@ class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
let shamt = 0;
let isCommutable = 1;
let Defs = DefRegs;
let neverHasSideEffects = 1;
}
class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
@ -582,6 +584,7 @@ class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
let rt = 0;
let shamt = 0;
let Uses = UseRegs;
let neverHasSideEffects = 1;
}
class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
@ -592,6 +595,7 @@ class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
let rd = 0;
let shamt = 0;
let Defs = DefRegs;
let neverHasSideEffects = 1;
}
class EffectiveAddress<string instr_asm, RegisterClass RC, Operand Mem> :
@ -635,6 +639,7 @@ class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
let rs = 0;
let shamt = sa;
let Predicates = [HasSwap];
let neverHasSideEffects = 1;
}
// Read Hardware