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Tidy up. 80 columns and some other spacing issues.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155291 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-04-21 18:13:35 +00:00
parent 0b5ad0b9d9
commit d0cf565e79
1 changed files with 9 additions and 7 deletions
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16
lib/Target/X86/X86ISelLowering.cpp
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@ -14888,6 +14888,7 @@ static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
N00.getOperand(0), N00.getOperand(1)),
DAG.getConstant(1, VT));
}
// Optimize vectors in AVX mode:
//
// v8i16 -> v8i32
@ -14902,15 +14903,17 @@ static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
//
if (Subtarget->hasAVX()) {
if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG);
SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG);
SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec,
DAG);
SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec,
DAG);
EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
VT.getVectorNumElements()/2);
EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
VT.getVectorNumElements()/2);
OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
@ -14919,7 +14922,6 @@ static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
}
}
return SDValue();
}