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Directly access objects which may change during compilation.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184121 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2013-06-17 20:41:25 +00:00
parent 99ccd5d5ef
commit d10fa8b1ca
6 changed files with 99 additions and 52 deletions
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10
include/llvm/CodeGen/MachineConstantPool.h
View File

@ -132,15 +132,17 @@ public:
/// address of the function constant pool values.
/// @brief The machine constant pool.
class MachineConstantPool {
const DataLayout *TD; ///< The machine's DataLayout.
unsigned PoolAlignment; ///< The alignment for the pool.
const TargetMachine &TM; ///< The target machine.
unsigned PoolAlignment; ///< The alignment for the pool.
std::vector<MachineConstantPoolEntry> Constants; ///< The pool of constants.
/// MachineConstantPoolValues that use an existing MachineConstantPoolEntry.
DenseSet<MachineConstantPoolValue*> MachineCPVsSharingEntries;
const DataLayout *getDataLayout() const;
public:
/// @brief The only constructor.
explicit MachineConstantPool(const DataLayout *td)
: TD(td), PoolAlignment(1) {}
explicit MachineConstantPool(const TargetMachine &TM)
: TM(TM), PoolAlignment(1) {}
~MachineConstantPool();
/// getConstantPoolAlignment - Return the alignment required by

13
include/llvm/CodeGen/MachineFrameInfo.h
View File

@ -27,6 +27,7 @@ class Type;
class MachineFunction;
class MachineBasicBlock;
class TargetFrameLowering;
class TargetMachine;
class BitVector;
class Value;
class AllocaInst;
@ -119,6 +120,8 @@ class MachineFrameInfo {
isSpillSlot(isSS), MayNeedSP(NSP), Alloca(Val), PreAllocated(false) {}
};
const TargetMachine &TM;
/// Objects - The list of stack objects allocated...
///
std::vector<StackObject> Objects;
@ -201,10 +204,6 @@ class MachineFrameInfo {
/// CSIValid - Has CSInfo been set yet?
bool CSIValid;
/// TargetFrameLowering - Target information about frame layout.
///
const TargetFrameLowering &TFI;
/// LocalFrameObjects - References to frame indices which are mapped
/// into the local frame allocation block. <FrameIdx, LocalOffset>
SmallVector<std::pair<int, int64_t>, 32> LocalFrameObjects;
@ -223,9 +222,11 @@ class MachineFrameInfo {
/// Whether the "realign-stack" option is on.
bool RealignOption;
const TargetFrameLowering *getFrameLowering() const;
public:
explicit MachineFrameInfo(const TargetFrameLowering &tfi, bool RealignOpt)
: TFI(tfi), RealignOption(RealignOpt) {
explicit MachineFrameInfo(const TargetMachine &TM, bool RealignOpt)
: TM(TM), RealignOption(RealignOpt) {
StackSize = NumFixedObjects = OffsetAdjustment = MaxAlignment = 0;
HasVarSizedObjects = false;
FrameAddressTaken = false;

21
include/llvm/CodeGen/MachineRegisterInfo.h
View File

@ -17,6 +17,7 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/CodeGen/MachineInstrBundle.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include <vector>
@ -26,7 +27,7 @@ namespace llvm {
/// registers, including vreg register classes, use/def chains for registers,
/// etc.
class MachineRegisterInfo {
const TargetRegisterInfo *const TRI;
const TargetMachine &TM;
/// IsSSA - True when the machine function is in SSA form and virtual
/// registers have a single def.
@ -57,6 +58,10 @@ class MachineRegisterInfo {
/// physical registers.
MachineOperand **PhysRegUseDefLists;
const TargetRegisterInfo *getTargetRegisterInfo() const {
return TM.getRegisterInfo();
}
/// getRegUseDefListHead - Return the head pointer for the register use/def
/// list for the specified virtual or physical register.
MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
@ -108,7 +113,7 @@ class MachineRegisterInfo {
MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
public:
explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
explicit MachineRegisterInfo(const TargetMachine &TM);
~MachineRegisterInfo();
//===--------------------------------------------------------------------===//
@ -377,7 +382,8 @@ public:
bool isPhysRegUsed(unsigned Reg) const {
if (UsedPhysRegMask.test(Reg))
return true;
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
Units.isValid(); ++Units)
if (UsedRegUnits.test(*Units))
return true;
return false;
@ -392,7 +398,8 @@ public:
/// setPhysRegUsed - Mark the specified register used in this function.
/// This should only be called during and after register allocation.
void setPhysRegUsed(unsigned Reg) {
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
Units.isValid(); ++Units)
UsedRegUnits.set(*Units);
}
@ -406,7 +413,8 @@ public:
/// This should only be called during and after register allocation.
void setPhysRegUnused(unsigned Reg) {
UsedPhysRegMask.reset(Reg);
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
Units.isValid(); ++Units)
UsedRegUnits.reset(*Units);
}
@ -466,7 +474,8 @@ public:
/// register, so a register allocator needs to track its liveness and
/// availability.
bool isAllocatable(unsigned PhysReg) const {
return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg);
return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
!isReserved(PhysReg);
}
//===--------------------------------------------------------------------===//

3
include/llvm/Target/TargetMachine.h
View File

@ -102,11 +102,14 @@ public:
void resetTargetOptions(const MachineFunction *MF) const;
// Interfaces to the major aspects of target machine information:
//
// -- Instruction opcode and operand information
// -- Pipelines and scheduling information
// -- Stack frame information
// -- Selection DAG lowering information
//
// N.B. These objects may change during compilation. It's not safe to cache
// them between functions.
virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
virtual const TargetLowering *getTargetLowering() const { return 0; }

53
lib/CodeGen/MachineFunction.cpp
View File

@ -55,23 +55,27 @@ MachineFunction::MachineFunction(const Function *F, const TargetMachine &TM,
GCModuleInfo* gmi)
: Fn(F), Target(TM), Ctx(mmi.getContext()), MMI(mmi), GMI(gmi) {
if (TM.getRegisterInfo())
RegInfo = new (Allocator) MachineRegisterInfo(*TM.getRegisterInfo());
RegInfo = new (Allocator) MachineRegisterInfo(TM);
else
RegInfo = 0;
MFInfo = 0;
FrameInfo = new (Allocator) MachineFrameInfo(*TM.getFrameLowering(),
TM.Options.RealignStack);
FrameInfo = new (Allocator) MachineFrameInfo(TM, TM.Options.RealignStack);
if (Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
Attribute::StackAlignment))
FrameInfo->ensureMaxAlignment(Fn->getAttributes().
getStackAlignment(AttributeSet::FunctionIndex));
ConstantPool = new (Allocator) MachineConstantPool(TM.getDataLayout());
ConstantPool = new (Allocator) MachineConstantPool(TM);
Alignment = TM.getTargetLowering()->getMinFunctionAlignment();
// FIXME: Shouldn't use pref alignment if explicit alignment is set on Fn.
if (!Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
Attribute::OptimizeForSize))
Alignment = std::max(Alignment,
TM.getTargetLowering()->getPrefFunctionAlignment());
FunctionNumber = FunctionNum;
JumpTableInfo = 0;
}
@ -457,11 +461,15 @@ MCSymbol *MachineFunction::getPICBaseSymbol() const {
// MachineFrameInfo implementation
//===----------------------------------------------------------------------===//
const TargetFrameLowering *MachineFrameInfo::getFrameLowering() const {
return TM.getFrameLowering();
}
/// ensureMaxAlignment - Make sure the function is at least Align bytes
/// aligned.
void MachineFrameInfo::ensureMaxAlignment(unsigned Align) {
if (!TFI.isStackRealignable() || !RealignOption)
assert(Align <= TFI.getStackAlignment() &&
if (!getFrameLowering()->isStackRealignable() || !RealignOption)
assert(Align <= getFrameLowering()->getStackAlignment() &&
"For targets without stack realignment, Align is out of limit!");
if (MaxAlignment < Align) MaxAlignment = Align;
}
@ -483,8 +491,10 @@ static inline unsigned clampStackAlignment(bool ShouldClamp, unsigned Align,
int MachineFrameInfo::CreateStackObject(uint64_t Size, unsigned Alignment,
bool isSS, bool MayNeedSP, const AllocaInst *Alloca) {
assert(Size != 0 && "Cannot allocate zero size stack objects!");
Alignment = clampStackAlignment(!TFI.isStackRealignable() || !RealignOption,
Alignment, TFI.getStackAlignment());
Alignment =
clampStackAlignment(!getFrameLowering()->isStackRealignable() ||
!RealignOption,
Alignment, getFrameLowering()->getStackAlignment());
Objects.push_back(StackObject(Size, Alignment, 0, false, isSS, MayNeedSP,
Alloca));
int Index = (int)Objects.size() - NumFixedObjects - 1;
@ -499,8 +509,10 @@ int MachineFrameInfo::CreateStackObject(uint64_t Size, unsigned Alignment,
///
int MachineFrameInfo::CreateSpillStackObject(uint64_t Size,
unsigned Alignment) {
Alignment = clampStackAlignment(!TFI.isStackRealignable() || !RealignOption,
Alignment, TFI.getStackAlignment());
Alignment =
clampStackAlignment(!getFrameLowering()->isStackRealignable() ||
!RealignOption,
Alignment, getFrameLowering()->getStackAlignment());
CreateStackObject(Size, Alignment, true, false);
int Index = (int)Objects.size() - NumFixedObjects - 1;
ensureMaxAlignment(Alignment);
@ -514,8 +526,10 @@ int MachineFrameInfo::CreateSpillStackObject(uint64_t Size,
///
int MachineFrameInfo::CreateVariableSizedObject(unsigned Alignment) {
HasVarSizedObjects = true;
Alignment = clampStackAlignment(!TFI.isStackRealignable() || !RealignOption,
Alignment, TFI.getStackAlignment());
Alignment =
clampStackAlignment(!getFrameLowering()->isStackRealignable() ||
!RealignOption,
Alignment, getFrameLowering()->getStackAlignment());
Objects.push_back(StackObject(0, Alignment, 0, false, false, true, 0));
ensureMaxAlignment(Alignment);
return (int)Objects.size()-NumFixedObjects-1;
@ -533,10 +547,12 @@ int MachineFrameInfo::CreateFixedObject(uint64_t Size, int64_t SPOffset,
// the incoming frame position. If the frame object is at offset 32 and
// the stack is guaranteed to be 16-byte aligned, then we know that the
// object is 16-byte aligned.
unsigned StackAlign = TFI.getStackAlignment();
unsigned StackAlign = getFrameLowering()->getStackAlignment();
unsigned Align = MinAlign(SPOffset, StackAlign);
Align = clampStackAlignment(!TFI.isStackRealignable() || !RealignOption,
Align, TFI.getStackAlignment());
Align =
clampStackAlignment(!getFrameLowering()->isStackRealignable() ||
!RealignOption,
Align, getFrameLowering()->getStackAlignment());
Objects.insert(Objects.begin(), StackObject(Size, Align, SPOffset, Immutable,
/*isSS*/ false,
/*NeedSP*/ false,
@ -770,6 +786,10 @@ void MachineJumpTableInfo::dump() const { print(dbgs()); }
void MachineConstantPoolValue::anchor() { }
const DataLayout *MachineConstantPool::getDataLayout() const {
return TM.getDataLayout();
}
Type *MachineConstantPoolEntry::getType() const {
if (isMachineConstantPoolEntry())
return Val.MachineCPVal->getType();
@ -851,7 +871,8 @@ unsigned MachineConstantPool::getConstantPoolIndex(const Constant *C,
// FIXME, this could be made much more efficient for large constant pools.
for (unsigned i = 0, e = Constants.size(); i != e; ++i)
if (!Constants[i].isMachineConstantPoolEntry() &&
CanShareConstantPoolEntry(Constants[i].Val.ConstVal, C, TD)) {
CanShareConstantPoolEntry(Constants[i].Val.ConstVal, C,
getDataLayout())) {
if ((unsigned)Constants[i].getAlignment() < Alignment)
Constants[i].Alignment = Alignment;
return i;

51
lib/CodeGen/MachineRegisterInfo.cpp
View File

@ -19,16 +19,18 @@
using namespace llvm;
MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
: TRI(&TRI), IsSSA(true), TracksLiveness(true) {
MachineRegisterInfo::MachineRegisterInfo(const TargetMachine &TM)
: TM(TM), IsSSA(true), TracksLiveness(true) {
VRegInfo.reserve(256);
RegAllocHints.reserve(256);
UsedRegUnits.resize(TRI.getNumRegUnits());
UsedPhysRegMask.resize(TRI.getNumRegs());
UsedRegUnits.resize(getTargetRegisterInfo()->getNumRegUnits());
UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs());
// Create the physreg use/def lists.
PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
PhysRegUseDefLists =
new MachineOperand*[getTargetRegisterInfo()->getNumRegs()];
memset(PhysRegUseDefLists, 0,
sizeof(MachineOperand*)*getTargetRegisterInfo()->getNumRegs());
}
MachineRegisterInfo::~MachineRegisterInfo() {
@ -50,7 +52,8 @@ MachineRegisterInfo::constrainRegClass(unsigned Reg,
const TargetRegisterClass *OldRC = getRegClass(Reg);
if (OldRC == RC)
return RC;
const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
const TargetRegisterClass *NewRC =
getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
if (!NewRC || NewRC == OldRC)
return NewRC;
if (NewRC->getNumRegs() < MinNumRegs)
@ -63,7 +66,8 @@ bool
MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterClass *OldRC = getRegClass(Reg);
const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
const TargetRegisterClass *NewRC =
getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC);
// Stop early if there is no room to grow.
if (NewRC == OldRC)
@ -73,14 +77,16 @@ MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
++I) {
const TargetRegisterClass *OpRC =
I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
I->getRegClassConstraint(I.getOperandNo(), TII,
getTargetRegisterInfo());
if (unsigned SubIdx = I.getOperand().getSubReg()) {
if (OpRC)
NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx);
NewRC = getTargetRegisterInfo()->getMatchingSuperRegClass(NewRC, OpRC,
SubIdx);
else
NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx);
NewRC = getTargetRegisterInfo()->getSubClassWithSubReg(NewRC, SubIdx);
} else if (OpRC)
NewRC = TRI->getCommonSubClass(NewRC, OpRC);
NewRC = getTargetRegisterInfo()->getCommonSubClass(NewRC, OpRC);
if (!NewRC || NewRC == OldRC)
return false;
}
@ -126,24 +132,28 @@ void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
MachineOperand *MO = &I.getOperand();
MachineInstr *MI = MO->getParent();
if (!MI) {
errs() << PrintReg(Reg, TRI) << " use list MachineOperand " << MO
errs() << PrintReg(Reg, getTargetRegisterInfo())
<< " use list MachineOperand " << MO
<< " has no parent instruction.\n";
Valid = false;
}
MachineOperand *MO0 = &MI->getOperand(0);
unsigned NumOps = MI->getNumOperands();
if (!(MO >= MO0 && MO < MO0+NumOps)) {
errs() << PrintReg(Reg, TRI) << " use list MachineOperand " << MO
errs() << PrintReg(Reg, getTargetRegisterInfo())
<< " use list MachineOperand " << MO
<< " doesn't belong to parent MI: " << *MI;
Valid = false;
}
if (!MO->isReg()) {
errs() << PrintReg(Reg, TRI) << " MachineOperand " << MO << ": " << *MO
errs() << PrintReg(Reg, getTargetRegisterInfo())
<< " MachineOperand " << MO << ": " << *MO
<< " is not a register\n";
Valid = false;
}
if (MO->getReg() != Reg) {
errs() << PrintReg(Reg, TRI) << " use-list MachineOperand " << MO << ": "
errs() << PrintReg(Reg, getTargetRegisterInfo())
<< " use-list MachineOperand " << MO << ": "
<< *MO << " is the wrong register\n";
Valid = false;
}
@ -156,7 +166,7 @@ void MachineRegisterInfo::verifyUseLists() const {
#ifndef NDEBUG
for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
verifyUseList(TargetRegisterInfo::index2VirtReg(i));
for (unsigned i = 1, e = TRI->getNumRegs(); i != e; ++i)
for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
verifyUseList(i);
#endif
}
@ -390,8 +400,8 @@ void MachineRegisterInfo::dumpUses(unsigned Reg) const {
#endif
void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
ReservedRegs = TRI->getReservedRegs(MF);
assert(ReservedRegs.size() == TRI->getNumRegs() &&
ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
"Invalid ReservedRegs vector from target");
}
@ -401,7 +411,8 @@ bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
// Check if any overlapping register is modified, or allocatable so it may be
// used later.
for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true);
AI.isValid(); ++AI)
if (!def_empty(*AI) || isAllocatable(*AI))
return false;
return true;