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Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the

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Machine-level API cleanup instigated by Chris.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2007-12-31 06:32:00 +00:00
parent f20c1a497f
commit d10fd9791c
31 changed files with 321 additions and 267 deletions
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10
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
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@@ -359,7 +359,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
} else {
// Create the reg, emit the copy.
VRBase = RegInfo.createVirtualRegister(TRC);
MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC);
TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC);
}
if (InstanceNo > 0)
@@ -751,7 +751,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
TRC =
MRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(),
InReg);
MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC);
TII->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC);
}
break;
}
@@ -848,7 +848,7 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseM
}
}
assert(I->Reg && "Unknown physical register!");
MRI->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
SU->CopyDstRC, SU->CopySrcRC);
} else {
// Copy from physical register.
@@ -856,7 +856,7 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseM
unsigned VRBase = RegInfo.createVirtualRegister(SU->CopyDstRC);
bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase));
assert(isNew && "Node emitted out of order - early");
MRI->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
SU->CopyDstRC, SU->CopySrcRC);
}
break;
@@ -874,7 +874,7 @@ void ScheduleDAG::EmitSchedule() {
E = RegInfo.livein_end(); LI != E; ++LI)
if (LI->second) {
const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second);
MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
TII->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
LI->first, RC, RC);
}
}