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https://github.com/c64scene-ar/llvm-6502.git
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Fix the handling of partial redefines in the fast register allocator.
A partial redefine needs to be treated like a tied operand, and the register must be reloaded while processing use operands. This fixes a bug where partially redefined registers were processed as normal defs with a reload added. The reload could clobber another use operand if it was a kill that allowed register reuse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107193 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
5d52165e4e
commit
d1303d2a66
@ -515,7 +515,6 @@ RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
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bool New;
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tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
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LiveReg &LR = LRI->second;
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bool PartialRedef = MI->getOperand(OpNum).getSubReg();
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if (New) {
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// If there is no hint, peek at the only use of this register.
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if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
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@ -527,15 +526,7 @@ RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
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Hint = DstReg;
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}
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allocVirtReg(MI, *LRI, Hint);
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// If this is only a partial redefinition, we must reload the other parts.
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if (PartialRedef && MI->readsVirtualRegister(VirtReg)) {
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const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
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int FI = getStackSpaceFor(VirtReg, RC);
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DEBUG(dbgs() << "Reloading for partial redef: %reg" << VirtReg << "\n");
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TII->loadRegFromStackSlot(*MBB, MI, LR.PhysReg, FI, RC, TRI);
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++NumLoads;
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}
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} else if (LR.LastUse && !PartialRedef) {
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} else if (LR.LastUse) {
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// Redefining a live register - kill at the last use, unless it is this
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// instruction defining VirtReg multiple times.
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if (LR.LastUse != MI || LR.LastUse->getOperand(LR.LastOpNum).isUse())
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@ -571,10 +562,16 @@ RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
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} else if (LR.Dirty) {
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if (isLastUseOfLocalReg(MO)) {
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DEBUG(dbgs() << "Killing last use: " << MO << "\n");
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MO.setIsKill();
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if (MO.isUse())
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MO.setIsKill();
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else
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MO.setIsDead();
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} else if (MO.isKill()) {
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DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n");
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MO.setIsKill(false);
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} else if (MO.isDead()) {
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DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n");
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MO.setIsDead(false);
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}
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} else if (MO.isKill()) {
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// We must remove kill flags from uses of reloaded registers because the
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@ -583,6 +580,9 @@ RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
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// This would cause a second reload of %x into a different register.
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DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n");
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MO.setIsKill(false);
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} else if (MO.isDead()) {
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DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n");
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MO.setIsDead(false);
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}
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assert(LR.PhysReg && "Register not assigned");
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LR.LastUse = MI;
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@ -625,7 +625,8 @@ void RAFast::handleThroughOperands(MachineInstr *MI,
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
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if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i)) {
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if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i) ||
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(MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
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if (ThroughRegs.insert(Reg))
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DEBUG(dbgs() << " %reg" << Reg);
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}
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@ -649,6 +650,7 @@ void RAFast::handleThroughOperands(MachineInstr *MI,
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}
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}
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SmallVector<unsigned, 8> PartialDefs;
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DEBUG(dbgs() << "Allocating tied uses and early clobbers.\n");
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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@ -663,6 +665,14 @@ void RAFast::handleThroughOperands(MachineInstr *MI,
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LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
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unsigned PhysReg = LRI->second.PhysReg;
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setPhysReg(MI, i, PhysReg);
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// Note: we don't update the def operand yet. That would cause the normal
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// def-scan to attempt spilling.
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} else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
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DEBUG(dbgs() << "Partial redefine: " << MO << "\n");
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// Reload the register, but don't assign to the operand just yet.
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// That would confuse the later phys-def processing pass.
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LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
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PartialDefs.push_back(LRI->second.PhysReg);
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} else if (MO.isEarlyClobber()) {
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// Note: defineVirtReg may invalidate MO.
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LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
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@ -683,6 +693,10 @@ void RAFast::handleThroughOperands(MachineInstr *MI,
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
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UsedInInstr.set(*AS);
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}
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// Also mark PartialDefs as used to avoid reallocation.
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for (unsigned i = 0, e = PartialDefs.size(); i != e; ++i)
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UsedInInstr.set(PartialDefs[i]);
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}
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void RAFast::AllocateBasicBlock() {
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@ -767,7 +781,10 @@ void RAFast::AllocateBasicBlock() {
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// Mark physreg uses and early clobbers as used.
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// Find the end of the virtreg operands
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unsigned VirtOpEnd = 0;
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bool hasTiedOps = false, hasEarlyClobbers = false, hasPhysDefs = false;
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bool hasTiedOps = false;
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bool hasEarlyClobbers = false;
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bool hasPartialRedefs = false;
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bool hasPhysDefs = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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@ -775,11 +792,15 @@ void RAFast::AllocateBasicBlock() {
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if (!Reg) continue;
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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VirtOpEnd = i+1;
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if (MO.isUse())
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if (MO.isUse()) {
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hasTiedOps = hasTiedOps ||
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TID.getOperandConstraint(i, TOI::TIED_TO) != -1;
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else if (MO.isEarlyClobber())
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hasEarlyClobbers = true;
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} else {
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if (MO.isEarlyClobber())
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hasEarlyClobbers = true;
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if (MO.getSubReg() && MI->readsVirtualRegister(Reg))
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hasPartialRedefs = true;
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}
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continue;
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}
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if (!Allocatable.test(Reg)) continue;
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@ -800,7 +821,8 @@ void RAFast::AllocateBasicBlock() {
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// operands.
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// We didn't detect inline asm tied operands above, so just make this extra
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// pass for all inline asm.
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if (MI->isInlineAsm() || hasEarlyClobbers || (hasTiedOps && hasPhysDefs)) {
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if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
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(hasTiedOps && hasPhysDefs)) {
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handleThroughOperands(MI, VirtDead);
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// Don't attempt coalescing when we have funny stuff going on.
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CopyDst = 0;
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22
test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
Normal file
22
test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
Normal file
@ -0,0 +1,22 @@
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; RUN: llc < %s -O0 -mcpu=cortex-a8 | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
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target triple = "thumbv7-apple-darwin10"
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; This tests the fast register allocator's handling of partial redefines:
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;
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; %reg1026<def> = VMOVv16i8 0, pred:14, pred:%reg0
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; %reg1028:dsub_1<def> = EXTRACT_SUBREG %reg1026<kill>, 1
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;
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; %reg1026 gets allocated %Q0, and if %reg1028 is reloaded for the partial redef,
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; it cannot also get %Q0.
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; CHECK: vmov.i8 q0, #0x0
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; CHECK-NOT: vld1.64 {d0,d1}
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; CHECK: vmov.f64 d3, d0
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define i32 @main(i32 %argc, i8** %argv) nounwind {
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entry:
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%0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 2> ; <<2 x i64>> [#uses=1]
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store <2 x i64> %0, <2 x i64>* undef, align 16
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ret i32 undef
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}
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