diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
index 0c07fd33405..37c85b37351 100644
--- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp
+++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
@@ -128,6 +128,7 @@ bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID,
   default:
     // All multi-slot instructions must come first.
     return NSlots > 1;
+  case PPC::Sched::IIC_BrCR: // cr logicals
   case PPC::Sched::IIC_SprMFCR:
   case PPC::Sched::IIC_SprMFCRF:
   case PPC::Sched::IIC_SprMTSPR:
diff --git a/lib/Target/PowerPC/PPCScheduleP7.td b/lib/Target/PowerPC/PPCScheduleP7.td
index 958bc90f674..a3670a55a04 100644
--- a/lib/Target/PowerPC/PPCScheduleP7.td
+++ b/lib/Target/PowerPC/PPCScheduleP7.td
@@ -137,8 +137,8 @@ def P7Itineraries : ProcessorItineraries<
   InstrItinData<IIC_BrB         , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
                                    InstrStage<1, [P7_BRU]>],
                                   [3, 1, 1]>,
-  InstrItinData<IIC_BrCR        , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
-                                   InstrStage<1, [P7_BRU]>],
+  InstrItinData<IIC_BrCR        , [InstrStage<1, [P7_DU1], 0>,
+                                   InstrStage<1, [P7_CRU]>],
                                   [3, 1, 1]>,
   InstrItinData<IIC_BrMCR       , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
                                    InstrStage<1, [P7_BRU]>],