From d151389bd1909103ae3063bf470eb4d44abab468 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Thu, 2 Jan 2014 21:38:26 +0000 Subject: [PATCH] [PPC] Fix the scheduling of CR logicals on the P7 CR logicals (crand, crxor, etc.) on the P7 need to be in the first slot of each dispatch group. The old itinerary entry was just wrong (but has not mattered because we don't generate these instructions). This will matter when, in an upcoming commit, we start generating these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198359 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCHazardRecognizers.cpp | 1 + lib/Target/PowerPC/PPCScheduleP7.td | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp index 0c07fd33405..37c85b37351 100644 --- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -128,6 +128,7 @@ bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, default: // All multi-slot instructions must come first. return NSlots > 1; + case PPC::Sched::IIC_BrCR: // cr logicals case PPC::Sched::IIC_SprMFCR: case PPC::Sched::IIC_SprMFCRF: case PPC::Sched::IIC_SprMTSPR: diff --git a/lib/Target/PowerPC/PPCScheduleP7.td b/lib/Target/PowerPC/PPCScheduleP7.td index 958bc90f674..a3670a55a04 100644 --- a/lib/Target/PowerPC/PPCScheduleP7.td +++ b/lib/Target/PowerPC/PPCScheduleP7.td @@ -137,8 +137,8 @@ def P7Itineraries : ProcessorItineraries< InstrItinData, InstrStage<1, [P7_BRU]>], [3, 1, 1]>, - InstrItinData, - InstrStage<1, [P7_BRU]>], + InstrItinData, + InstrStage<1, [P7_CRU]>], [3, 1, 1]>, InstrItinData, InstrStage<1, [P7_BRU]>],