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R600/SI: Use pseudo instruction for fabs/clamp/fneg

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208478 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune 2014-05-10 19:18:25 +00:00
parent bfd5dad4c9
commit d19e830174
2 changed files with 74 additions and 4 deletions
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44
lib/Target/R600/SIISelLowering.cpp
View File

@ -539,6 +539,50 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MIB.addOperand(MI->getOperand(i));
MI->eraseFromParent();
break;
}
case AMDGPU::FABS_SI: {
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
Reg)
.addImm(0x7fffffff);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_AND_B32_e32),
MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addReg(Reg);
MI->eraseFromParent();
break;
}
case AMDGPU::FNEG_SI: {
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
Reg)
.addImm(0x80000000);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_XOR_B32_e32),
MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addReg(Reg);
MI->eraseFromParent();
break;
}
case AMDGPU::FCLAMP_SI: {
const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F32_e64),
MI->getOperand(0).getReg())
.addOperand(MI->getOperand(1))
.addImm(0) // SRC1
.addImm(0) // ABS
.addImm(1) // CLAMP
.addImm(0) // OMOD
.addImm(0); // NEG
MI->eraseFromParent();
}
}
return BB;

34
lib/Target/R600/SIInstructions.td
View File

@ -1951,10 +1951,18 @@ def : BitConvert <v16f32, v16i32, VReg_512>;
/********** Src & Dst modifiers **********/
/********** =================== **********/
def FCLAMP_SI : AMDGPUShaderInst <
(outs VReg_32:$dst),
(ins VSrc_32:$src0),
"FCLAMP_SI $dst, $src0",
[]
> {
let usesCustomInserter = 1;
}
def : Pat <
(int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
(V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
(FCLAMP_SI f32:$src)
>;
/********** ================================ **********/
@ -1973,14 +1981,32 @@ def : Pat <
(V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
>;
def FABS_SI : AMDGPUShaderInst <
(outs VReg_32:$dst),
(ins VSrc_32:$src0),
"FABS_SI $dst, $src0",
[]
> {
let usesCustomInserter = 1;
}
def : Pat <
(fabs f32:$src),
(V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff)) /* Clear sign bit */
(FABS_SI f32:$src)
>;
def FNEG_SI : AMDGPUShaderInst <
(outs VReg_32:$dst),
(ins VSrc_32:$src0),
"FNEG_SI $dst, $src0",
[]
> {
let usesCustomInserter = 1;
}
def : Pat <
(fneg f32:$src),
(V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Toggle sign bit */
(FNEG_SI f32:$src)
>;
/********** ================== **********/