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R600/SI: Use pseudo instruction for fabs/clamp/fneg

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208478 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune
2014-05-10 19:18:25 +00:00
parent bfd5dad4c9
commit d19e830174
2 changed files with 74 additions and 4 deletions
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44
lib/Target/R600/SIISelLowering.cpp
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@@ -539,6 +539,50 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MIB.addOperand(MI->getOperand(i));
MI->eraseFromParent();
break;
}
case AMDGPU::FABS_SI: {
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
Reg)
.addImm(0x7fffffff);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_AND_B32_e32),
MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addReg(Reg);
MI->eraseFromParent();
break;
}
case AMDGPU::FNEG_SI: {
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
Reg)
.addImm(0x80000000);
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_XOR_B32_e32),
MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addReg(Reg);
MI->eraseFromParent();
break;
}
case AMDGPU::FCLAMP_SI: {
const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F32_e64),
MI->getOperand(0).getReg())
.addOperand(MI->getOperand(1))
.addImm(0) // SRC1
.addImm(0) // ABS
.addImm(1) // CLAMP
.addImm(0) // OMOD
.addImm(0); // NEG
MI->eraseFromParent();
}
}
return BB;