mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-02 07:11:49 +00:00
Struct byval cleanup: add helper functions to reduce code duplication.
Helper functions are added: emitPostLd: emit a post-increment load operation with given size. emitPostSt: emit a post-increment store operation with given size. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193656 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Manman Ren
parent
4598b40ce6
commit
d1ea5928dd
@ -7248,6 +7248,106 @@ MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
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llvm_unreachable("Expecting a BB with two successors!");
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}
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/// Return the load opcode for a given load size. If load size >= 8,
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/// neon opcode will be returned.
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static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) {
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if (LdSize >= 8)
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return LdSize == 16 ? ARM::VLD1q32wb_fixed
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: LdSize == 8 ? ARM::VLD1d32wb_fixed : 0;
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if (IsThumb1)
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return LdSize == 4 ? ARM::tLDRi
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: LdSize == 2 ? ARM::tLDRHi
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: LdSize == 1 ? ARM::tLDRBi : 0;
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if (IsThumb2)
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return LdSize == 4 ? ARM::t2LDR_POST
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: LdSize == 2 ? ARM::t2LDRH_POST
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: LdSize == 1 ? ARM::t2LDRB_POST : 0;
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return LdSize == 4 ? ARM::LDR_POST_IMM
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: LdSize == 2 ? ARM::LDRH_POST
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: LdSize == 1 ? ARM::LDRB_POST_IMM : 0;
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}
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/// Return the store opcode for a given store size. If store size >= 8,
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/// neon opcode will be returned.
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static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) {
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if (StSize >= 8)
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return StSize == 16 ? ARM::VST1q32wb_fixed
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: StSize == 8 ? ARM::VST1d32wb_fixed : 0;
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if (IsThumb1)
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return StSize == 4 ? ARM::tSTRi
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: StSize == 2 ? ARM::tSTRHi
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: StSize == 1 ? ARM::tSTRBi : 0;
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if (IsThumb2)
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return StSize == 4 ? ARM::t2STR_POST
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: StSize == 2 ? ARM::t2STRH_POST
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: StSize == 1 ? ARM::t2STRB_POST : 0;
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return StSize == 4 ? ARM::STR_POST_IMM
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: StSize == 2 ? ARM::STRH_POST
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: StSize == 1 ? ARM::STRB_POST_IMM : 0;
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}
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/// Emit a post-increment load operation with given size. The instructions
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/// will be added to BB at Pos.
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static void emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos,
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const TargetInstrInfo *TII, DebugLoc dl,
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unsigned LdSize, unsigned Data, unsigned AddrIn,
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unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
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unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2);
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assert(LdOpc != 0 && "Should have a load opcode");
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if (LdSize >= 8) {
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AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
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.addReg(AddrOut, RegState::Define).addReg(AddrIn)
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.addImm(0));
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} else if (IsThumb1) {
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// load + update AddrIn
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AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
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.addReg(AddrIn).addImm(0));
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MachineInstrBuilder MIB =
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BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(AddrIn).addImm(LdSize);
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AddDefaultPred(MIB);
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} else if (IsThumb2) {
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AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
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.addReg(AddrOut, RegState::Define).addReg(AddrIn)
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.addImm(LdSize));
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} else { // arm
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AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
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.addReg(AddrOut, RegState::Define).addReg(AddrIn)
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.addReg(0).addImm(LdSize));
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}
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}
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/// Emit a post-increment store operation with given size. The instructions
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/// will be added to BB at Pos.
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static void emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos,
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const TargetInstrInfo *TII, DebugLoc dl,
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unsigned StSize, unsigned Data, unsigned AddrIn,
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unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
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unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2);
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assert(StOpc != 0 && "Should have a store opcode");
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if (StSize >= 8) {
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AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
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.addReg(AddrIn).addImm(0).addReg(Data));
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} else if (IsThumb1) {
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// store + update AddrIn
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AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc)).addReg(Data)
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.addReg(AddrIn).addImm(0));
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MachineInstrBuilder MIB =
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BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(AddrIn).addImm(StSize);
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AddDefaultPred(MIB);
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} else if (IsThumb2) {
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AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
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.addReg(Data).addReg(AddrIn).addImm(StSize));
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} else { // arm
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AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
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.addReg(Data).addReg(AddrIn).addReg(0)
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.addImm(StSize));
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}
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}
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MachineBasicBlock *
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ARMTargetLowering::EmitStructByval(MachineInstr *MI,
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MachineBasicBlock *BB) const {
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@ -7268,8 +7368,6 @@ ARMTargetLowering::EmitStructByval(MachineInstr *MI,
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned UnitSize = 0;
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unsigned UnitLdOpc = 0;
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unsigned UnitStOpc = 0;
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const TargetRegisterClass *TRC = 0;
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const TargetRegisterClass *VecTRC = 0;
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@ -7300,43 +7398,12 @@ ARMTargetLowering::EmitStructByval(MachineInstr *MI,
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bool IsNeon = UnitSize >= 8;
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TRC = (IsThumb1 || IsThumb2) ? (const TargetRegisterClass *)&ARM::tGPRRegClass
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: (const TargetRegisterClass *)&ARM::GPRRegClass;
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if (IsNeon) {
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UnitLdOpc = UnitSize == 16 ? ARM::VLD1q32wb_fixed
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: UnitSize == 8 ? ARM::VLD1d32wb_fixed : 0;
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UnitStOpc = UnitSize == 16 ? ARM::VST1q32wb_fixed
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: UnitSize == 8 ? ARM::VST1d32wb_fixed : 0;
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if (IsNeon)
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VecTRC = UnitSize == 16
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? (const TargetRegisterClass *)&ARM::DPairRegClass
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: UnitSize == 8
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? (const TargetRegisterClass *)&ARM::DPRRegClass
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: 0;
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} else if (IsThumb1) {
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UnitLdOpc = UnitSize == 4 ? ARM::tLDRi
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: UnitSize == 2 ? ARM::tLDRHi
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: UnitSize == 1 ? ARM::tLDRBi : 0;
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UnitStOpc = UnitSize == 4 ? ARM::tSTRi
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: UnitSize == 2 ? ARM::tSTRHi
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: UnitSize == 1 ? ARM::tSTRBi : 0;
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} else if (IsThumb2) {
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UnitLdOpc = UnitSize == 4
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? ARM::t2LDR_POST
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: UnitSize == 2 ? ARM::t2LDRH_POST
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: UnitSize == 1 ? ARM::t2LDRB_POST : 0;
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UnitStOpc = UnitSize == 4
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? ARM::t2STR_POST
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: UnitSize == 2 ? ARM::t2STRH_POST
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: UnitSize == 1 ? ARM::t2STRB_POST : 0;
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} else {
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UnitLdOpc = UnitSize == 4
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? ARM::LDR_POST_IMM
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: UnitSize == 2 ? ARM::LDRH_POST
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: UnitSize == 1 ? ARM::LDRB_POST_IMM : 0;
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UnitStOpc = UnitSize == 4
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? ARM::STR_POST_IMM
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: UnitSize == 2 ? ARM::STRH_POST
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: UnitSize == 1 ? ARM::STRB_POST_IMM : 0;
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}
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assert(UnitLdOpc != 0 && UnitStOpc != 0 && "Should have unit opcodes");
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unsigned BytesLeft = SizeVal % UnitSize;
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unsigned LoopSize = SizeVal - BytesLeft;
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@ -7351,44 +7418,10 @@ ARMTargetLowering::EmitStructByval(MachineInstr *MI,
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unsigned srcOut = MRI.createVirtualRegister(TRC);
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unsigned destOut = MRI.createVirtualRegister(TRC);
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unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
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if (IsNeon) {
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(UnitLdOpc), scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn)
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.addImm(0));
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(UnitStOpc), destOut)
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.addReg(destIn).addImm(0).addReg(scratch));
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} else if (IsThumb1) {
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// load + update srcIn
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(UnitLdOpc), scratch)
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.addReg(srcIn).addImm(0));
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MachineInstrBuilder MIB =
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BuildMI(*BB, MI, dl, TII->get(ARM::tADDi8), srcOut);
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(srcIn).addImm(UnitSize);
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AddDefaultPred(MIB);
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// store + update destIn
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(UnitStOpc)).addReg(scratch)
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.addReg(destIn).addImm(0));
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MIB = BuildMI(*BB, MI, dl, TII->get(ARM::tADDi8), destOut);
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(destIn).addImm(UnitSize);
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AddDefaultPred(MIB);
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} else if (IsThumb2) {
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(UnitLdOpc), scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn)
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.addImm(UnitSize));
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(UnitStOpc), destOut)
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.addReg(scratch).addReg(destIn).addImm(UnitSize));
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} else { // arm
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(UnitLdOpc), scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn)
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.addReg(0).addImm(UnitSize));
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(UnitStOpc), destOut)
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.addReg(scratch).addReg(destIn).addReg(0)
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.addImm(UnitSize));
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}
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emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
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IsThumb1, IsThumb2);
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emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
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IsThumb1, IsThumb2);
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srcIn = srcOut;
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destIn = destOut;
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}
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@ -7400,41 +7433,10 @@ ARMTargetLowering::EmitStructByval(MachineInstr *MI,
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unsigned srcOut = MRI.createVirtualRegister(TRC);
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unsigned destOut = MRI.createVirtualRegister(TRC);
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unsigned scratch = MRI.createVirtualRegister(TRC);
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if (IsThumb1) {
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// load into scratch
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tLDRBi), scratch)
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.addReg(srcIn).addImm(0));
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// update base pointer
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MachineInstrBuilder MIB =
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BuildMI(*BB, MI, dl, TII->get(ARM::tADDi8), srcOut);
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(srcIn).addImm(1);
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AddDefaultPred(MIB);
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// store
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tSTRBi))
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.addReg(scratch).addReg(destIn).addImm(0));
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// update base pointer
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MIB = BuildMI(*BB, MI, dl, TII->get(ARM::tADDi8), destOut);
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(destIn).addImm(1);
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AddDefaultPred(MIB);
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} else if (IsThumb2) {
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::t2LDRB_POST), scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn)
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.addImm(1));
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::t2STRB_POST), destOut)
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.addReg(scratch).addReg(destIn).addImm(1));
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} else { // arm
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AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::LDRB_POST_IMM),
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scratch).addReg(srcOut, RegState::Define)
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.addReg(srcIn).addReg(0).addImm(1));
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AddDefaultPred(
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BuildMI(*BB, MI, dl, TII->get(ARM::STRB_POST_IMM), destOut)
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.addReg(scratch).addReg(destIn).addReg(0).addImm(1));
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}
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emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
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IsThumb1, IsThumb2);
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emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
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IsThumb1, IsThumb2);
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srcIn = srcOut;
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destIn = destOut;
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}
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@ -7531,44 +7533,10 @@ ARMTargetLowering::EmitStructByval(MachineInstr *MI,
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// [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
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// [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
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unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
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if (IsNeon) {
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AddDefaultPred(BuildMI(*BB, BB->end(), dl, TII->get(UnitLdOpc), scratch)
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.addReg(srcLoop, RegState::Define).addReg(srcPhi)
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.addImm(0));
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AddDefaultPred(BuildMI(*BB, BB->end(), dl, TII->get(UnitStOpc), destLoop)
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.addReg(destPhi).addImm(0).addReg(scratch));
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} else if (IsThumb1) {
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// load + update srcIn
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AddDefaultPred(BuildMI(*BB, BB->end(), dl, TII->get(UnitLdOpc), scratch)
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.addReg(srcPhi).addImm(0));
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MachineInstrBuilder MIB =
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BuildMI(*BB, BB->end(), dl, TII->get(ARM::tADDi8), srcLoop);
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(srcPhi).addImm(UnitSize);
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AddDefaultPred(MIB);
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// store + update destIn
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AddDefaultPred(BuildMI(*BB, BB->end(), dl, TII->get(UnitStOpc))
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.addReg(scratch).addReg(destPhi).addImm(0));
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MIB = BuildMI(*BB, BB->end(), dl, TII->get(ARM::tADDi8), destLoop);
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(destPhi).addImm(UnitSize);
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AddDefaultPred(MIB);
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} else if (IsThumb2) {
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AddDefaultPred(BuildMI(*BB, BB->end(), dl, TII->get(UnitLdOpc), scratch)
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.addReg(srcLoop, RegState::Define).addReg(srcPhi)
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.addImm(UnitSize));
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AddDefaultPred(BuildMI(*BB, BB->end(), dl, TII->get(UnitStOpc), destLoop)
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.addReg(scratch).addReg(destPhi).addImm(UnitSize));
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} else { // arm
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AddDefaultPred(BuildMI(*BB, BB->end(), dl, TII->get(UnitLdOpc), scratch)
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.addReg(srcLoop, RegState::Define).addReg(srcPhi)
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.addReg(0).addImm(UnitSize));
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AddDefaultPred(BuildMI(*BB, BB->end(), dl, TII->get(UnitStOpc), destLoop)
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.addReg(scratch).addReg(destPhi).addReg(0)
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.addImm(UnitSize));
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}
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emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
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IsThumb1, IsThumb2);
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emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
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IsThumb1, IsThumb2);
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// Decrement loop variable by UnitSize.
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if (IsThumb1) {
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@ -7605,41 +7573,10 @@ ARMTargetLowering::EmitStructByval(MachineInstr *MI,
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unsigned srcOut = MRI.createVirtualRegister(TRC);
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unsigned destOut = MRI.createVirtualRegister(TRC);
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unsigned scratch = MRI.createVirtualRegister(TRC);
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if (IsThumb1) {
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// load into scratch
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AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(ARM::tLDRBi),
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scratch).addReg(srcIn).addImm(0));
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// update base pointer
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MachineInstrBuilder MIB =
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BuildMI(*BB, StartOfExit, dl, TII->get(ARM::tADDi8), srcOut);
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(srcIn).addImm(1);
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AddDefaultPred(MIB);
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// store
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AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(ARM::tSTRBi))
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.addReg(scratch).addReg(destIn).addImm(0));
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// update base pointer
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MIB = BuildMI(*BB, StartOfExit, dl, TII->get(ARM::tADDi8), destOut);
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(destIn).addImm(1);
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AddDefaultPred(MIB);
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} else if (IsThumb2) {
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AddDefaultPred(
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BuildMI(*BB, StartOfExit, dl, TII->get(ARM::t2LDRB_POST), scratch)
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.addReg(srcOut, RegState::Define).addReg(srcIn).addImm(1));
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AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(ARM::t2STRB_POST),
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destOut).addReg(scratch).addReg(destIn).addImm(1));
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} else { // arm
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AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(ARM::LDRB_POST_IMM),
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scratch).addReg(srcOut, RegState::Define)
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.addReg(srcIn).addReg(0).addImm(1));
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AddDefaultPred(
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BuildMI(*BB, StartOfExit, dl, TII->get(ARM::STRB_POST_IMM), destOut)
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.addReg(scratch).addReg(destIn).addReg(0).addImm(1));
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}
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emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
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IsThumb1, IsThumb2);
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emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
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IsThumb1, IsThumb2);
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srcIn = srcOut;
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destIn = destOut;
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}
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