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AVX-512: Added TB prefix to all instructions without prefixes,
otherwise encoding fails after the last change in X86MCCodeEmitter.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191812 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
fd1b799eb9
commit
d243c19c1f
@ -742,11 +742,11 @@ multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
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defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
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"vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
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SSEPackedSingle>, TB, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
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SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
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"vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
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SSEPackedDouble>, TB, OpSize, EVEX_4V, VEX_W, EVEX_V512,
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SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
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EVEX_CD8<64, CD8VF>;
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def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
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@ -1044,7 +1044,7 @@ defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
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EVEX_CD8<64, CD8VF>;
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defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
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"vmovups", SSEPackedSingle>,
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TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
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"vmovupd", SSEPackedDouble>,
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OpSize, EVEX_V512, VEX_W,
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@ -1052,23 +1052,21 @@ defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
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def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
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"vmovaps\t{$src, $dst|$dst, $src}",
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[(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
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SSEPackedSingle>, EVEX, EVEX_V512, TB,
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EVEX_CD8<32, CD8VF>;
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SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
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def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
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"vmovapd\t{$src, $dst|$dst, $src}",
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[(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
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SSEPackedDouble>, EVEX, EVEX_V512,
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OpSize, TB, VEX_W, EVEX_CD8<64, CD8VF>;
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OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
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def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
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"vmovups\t{$src, $dst|$dst, $src}",
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[(store (v16f32 VR512:$src), addr:$dst)],
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SSEPackedSingle>, EVEX, EVEX_V512, TB,
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EVEX_CD8<32, CD8VF>;
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SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
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def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
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"vmovupd\t{$src, $dst|$dst, $src}",
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[(store (v8f64 VR512:$src), addr:$dst)],
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SSEPackedDouble>, EVEX, EVEX_V512,
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OpSize, TB, VEX_W, EVEX_CD8<64, CD8VF>;
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OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
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// Use vmovaps/vmovups for AVX-512 integer load/store.
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// 512-bit load/store
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@ -1234,7 +1232,7 @@ def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs),
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"vmovq{z}\t{$src, $dst|$dst, $src}",
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[(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
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addr:$dst)], IIC_SSE_MOVDQ>,
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EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
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EVEX, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
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Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
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// Move Scalar Single to Double Int
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@ -1589,13 +1587,13 @@ multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
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(outs RC:$dst), (ins RC:$src1, RC:$src2),
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asm, [(set RC:$dst,
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(vt (OpNode RC:$src1, RC:$src2)))],
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d>, EVEX_4V, TB;
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d>, EVEX_4V;
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def rm : AVX512PI<opc, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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asm, [(set RC:$dst,
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(vt (OpNode RC:$src1,
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(bitconvert (mem_frag addr:$src2)))))],
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d>, EVEX_4V, TB;
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d>, EVEX_4V;
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}
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defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
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@ -1742,19 +1740,19 @@ multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
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def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
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EVEX_4V;
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EVEX_4V, TB;
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let mayLoad = 1 in {
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def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
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itins.rm, d>, EVEX_4V;
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itins.rm, d>, EVEX_4V, TB;
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def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86scalar_mop:$src2),
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!strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
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", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
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[(set RC:$dst, (OpNode RC:$src1,
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(vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
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itins.rm, d>, EVEX_4V, EVEX_B;
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itins.rm, d>, EVEX_4V, EVEX_B, TB;
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}
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}
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@ -3016,14 +3014,14 @@ multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
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(i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
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EVEX_4V, TB, Sched<[WriteShuffleLd, ReadAfterLd]>;
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EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
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def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, i8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
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(i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
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EVEX_4V, TB, Sched<[WriteShuffle]>;
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EVEX_4V, Sched<[WriteShuffle]>;
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}
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defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
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@ -646,7 +646,7 @@ class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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Requires<[HasAVX512]>;
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class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>,
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB,
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Requires<[HasAVX512]>;
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class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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@ -658,10 +658,10 @@ class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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Requires<[HasAVX512]>;
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class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
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: Ii8<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
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class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin, d>, Requires<[HasAVX512]>;
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: I<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
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class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag>pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin>, T8,
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