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R600/SI: Add double precision fsub pattern for SI

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Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186179 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2013-07-12 18:15:08 +00:00
parent 54453c11b4
commit d2442c10f9
3 changed files with 42 additions and 3 deletions
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15
lib/Target/R600/SIISelLowering.cpp
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@@ -296,6 +296,21 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MI->eraseFromParent();
break;
}
case AMDGPU::V_SUB_F64: {
const SIInstrInfo *TII =
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64),
MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addReg(MI->getOperand(2).getReg())
.addImm(0) /* src2 */
.addImm(0) /* ABS */
.addImm(0) /* CLAMP */
.addImm(0) /* OMOD */
.addImm(2); /* NEG */
MI->eraseFromParent();
break;
}
}
return BB;
}