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Fix a miscompilation caused by a typo. When turning a adde with negative value

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into a sbc with a positive number, the immediate should be complemented, not
negated. Also added a missing pattern for ARM codegen.

rdar://12559385


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166613 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2012-10-24 19:53:01 +00:00
parent 8c65549318
commit d258eb3ec5
4 changed files with 33 additions and 7 deletions
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12
lib/Target/ARM/ARMInstrInfo.td
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@ -283,15 +283,13 @@ class RegConstraint<string C> {
// ARM specific transformation functions and pattern fragments.
//
// imm_neg_XFORM - Return a imm value packed into the format described for
// imm_neg defs below.
// imm_neg_XFORM - Return the negation of an i32 immediate value.
def imm_neg_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
}]>;
// so_imm_not_XFORM - Return a so_imm value packed into the format described for
// so_imm_not def below.
def so_imm_not_XFORM : SDNodeXForm<imm, [{
// imm_not_XFORM - Return the complement of a i32 immediate value.
def imm_not_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
}]>;
@ -314,7 +312,7 @@ def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
}], so_imm_not_XFORM> {
}], imm_not_XFORM> {
let ParserMatchClass = so_imm_not_asmoperand;
}
@ -3120,6 +3118,8 @@ def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
// for part of the negation.
def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
(SBCri GPR:$src, so_imm_not:$imm)>;
def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
(SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
// Note: These are implemented in C++ code, because they have to generate
// ADD/SUBrs instructions, which use a complex pattern that a xform function

2
lib/Target/ARM/ARMInstrThumb2.td
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@ -1953,7 +1953,7 @@ def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
(t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR),
(t2SBCrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
(t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>;
// Select Bytes -- for disassembly only

13
test/CodeGen/ARM/carry.ll
View File

@ -45,3 +45,16 @@ entry:
%0 = sub nsw i64 0, %x
ret i64 %0
}
; rdar://12559385
define i64 @f5(i32 %vi) {
entry:
; CHECK: f5:
; CHECK: movw [[REG:r[0-9]+]], #36102
; CHECK: sbc r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]
%v0 = zext i32 %vi to i64
%v1 = xor i64 %v0, -155057456198619
%v4 = add i64 %v1, 155057456198619
%v5 = add i64 %v4, %v1
ret i64 %v5
}

13
test/CodeGen/Thumb2/carry.ll
View File

@ -20,3 +20,16 @@ entry:
%tmp2 = sub i64 %tmp1, %b
ret i64 %tmp2
}
; rdar://12559385
define i64 @f3(i32 %vi) {
entry:
; CHECK: f3:
; CHECK: movw [[REG:r[0-9]+]], #36102
; CHECK: sbcs r{{[0-9]+}}, [[REG]]
%v0 = zext i32 %vi to i64
%v1 = xor i64 %v0, -155057456198619
%v4 = add i64 %v1, 155057456198619
%v5 = add i64 %v4, %v1
ret i64 %v5
}