6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-02 07:11:49 +00:00
Code Issues Projects Releases Wiki Activity

getPostIndexedAddressParts change: passes in load/store instead of its loaded / stored VT.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31584 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-11-09 04:29:46 +00:00
parent a1fd6504aa
commit d258efaf6e
2 changed files with 2 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/Target/TargetLowering.h
View File

@ -385,7 +385,7 @@ public:
/// getPostIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if this node can be
/// combined with a load / store to form a post-indexed load / store.
virtual bool getPostIndexedAddressParts(SDNode *N, MVT::ValueType VT,
virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
SDOperand &Base, SDOperand &Offset,
ISD::MemOpAddrMode &AM,
SelectionDAG &DAG) {

4
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -282,10 +282,8 @@ namespace {
MVT::ValueType VT;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
VT = LD->getLoadedVT();
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
Ptr = ST->getBasePtr();
VT = ST->getStoredVT();
isLoad = false;
} else
return false;
@ -301,7 +299,7 @@ namespace {
SDOperand BasePtr;
SDOperand Offset;
ISD::MemOpAddrMode AM = ISD::UNINDEXED;
if (TLI.getPostIndexedAddressParts(Op, VT, BasePtr, Offset, AM,DAG)) {
if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM,DAG)) {
if (Ptr == Offset)
std::swap(BasePtr, Offset);
if (Ptr != BasePtr)