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[AVX512] Enable FP arithmetic lowering for AVX512VL subsets.

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Added RegOp2MemOpTable4 to transform 4th operand from register to memory in merge-masked versions of instructions. 
Added lowering tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224516 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Khasanov
2014-12-18 12:28:22 +00:00
parent e22e2b8798
commit d25d7bb372
6 changed files with 798 additions and 2 deletions
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3
lib/Target/X86/X86ISelLowering.cpp
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@@ -6213,7 +6213,8 @@ static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
if (!IsLoad)
return SDValue();
if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
(Subtarget->hasVLX() && ScalarSize == 64))
return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
// The integer check is needed for the 64-bit into 128-bit so it doesn't match