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X86: cvtpi2ps is just an SSE instruction with MMX operands. It has no AVX equivalent.

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Give it the right register format so we can also emit it when AVX is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183971 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2013-06-14 09:31:41 +00:00
parent ea3e57d0a1
commit d25ec760cb
2 changed files with 16 additions and 7 deletions
lib/Target/X86
X86InstrMMX.td
test/CodeGen/X86
mmx-builtins.ll

15
lib/Target/X86/X86InstrMMX.td

@ -189,13 +189,14 @@ multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
PatFrag ld_frag, string asm, Domain d> {
def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst),(ins DstRC:$src1, SrcRC:$src2),
asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
NoItinerary, d>;
def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
(ins DstRC:$src1, x86memop:$src2), asm,
[(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
NoItinerary, d>;
def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
(ins DstRC:$src1, SrcRC:$src2), asm,
[(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
NoItinerary, d>;
def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
(ins DstRC:$src1, x86memop:$src2), asm,
[(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
NoItinerary, d>;
}
//===----------------------------------------------------------------------===//

8
test/CodeGen/X86/mmx-builtins.ll

@ -1337,3 +1337,11 @@ entry:
%7 = extractelement <1 x i64> %6, i32 0
ret i64 %7
}
define <4 x float> @test89(<4 x float> %a, x86_mmx %b) nounwind {
; CHECK: cvtpi2ps
%c = tail call <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> %a, x86_mmx %b)
ret <4 x float> %c
}
declare <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float>, x86_mmx) nounwind readnone