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Fix <rdar://problem/8282498> even if it doesn't reproduce on trunk.

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When a register is defined by a partial load:

  %reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234

That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.

This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110874 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-08-11 23:08:22 +00:00
parent cf6abd2486
commit d29583bd32
1 changed files with 5 additions and 0 deletions
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5
lib/Target/X86/X86InstrInfo.cpp
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@ -2410,6 +2410,11 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
} else if (Ops.size() != 1) } else if (Ops.size() != 1)
return NULL; return NULL;
// Make sure the subregisters match.
// Otherwise we risk changing the size of the load.
if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
return NULL;
SmallVector<MachineOperand,X86::AddrNumOperands> MOs; SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
switch (LoadMI->getOpcode()) { switch (LoadMI->getOpcode()) {
case X86::V_SET0PS: case X86::V_SET0PS: