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[mips][msa] Expand all truncstores and loadexts for MSA as well as DSP

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191496 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2013-09-27 09:44:59 +00:00
parent 86f309b4d1
commit d2a31a124f
3 changed files with 48 additions and 14 deletions
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30
lib/Target/Mips/MipsSEISelLowering.cpp
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@ -41,6 +41,22 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
if (HasMips64) if (HasMips64)
addRegisterClass(MVT::i64, &Mips::GPR64RegClass); addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
if (Subtarget->hasDSP() || Subtarget->hasMSA()) {
// Expand all truncating stores and extending loads.
unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
setTruncStoreAction((MVT::SimpleValueType)VT0,
(MVT::SimpleValueType)VT1, Expand);
setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
}
}
if (Subtarget->hasDSP()) { if (Subtarget->hasDSP()) {
MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
@ -58,20 +74,6 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::BITCAST, VecTys[i], Legal); setOperationAction(ISD::BITCAST, VecTys[i], Legal);
} }
// Expand all truncating stores and extending loads.
unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
setTruncStoreAction((MVT::SimpleValueType)VT0,
(MVT::SimpleValueType)VT1, Expand);
setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
}
setTargetDAGCombine(ISD::SHL); setTargetDAGCombine(ISD::SHL);
setTargetDAGCombine(ISD::SRA); setTargetDAGCombine(ISD::SRA);
setTargetDAGCombine(ISD::SRL); setTargetDAGCombine(ISD::SRL);

11
test/CodeGen/Mips/msa/basic_operations.ll
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@ -1,5 +1,6 @@
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck -check-prefix=MIPS32 %s ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck -check-prefix=MIPS32 %s
@v4i8 = global <4 x i8> <i8 0, i8 0, i8 0, i8 0>
@v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> @v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
@v8i16 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> @v8i16 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
@v4i32 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0> @v4i32 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>
@ -454,3 +455,13 @@ define void @insert_v2i64(i64 %a) nounwind {
ret void ret void
; MIPS32: .size insert_v2i64 ; MIPS32: .size insert_v2i64
} }
define void @truncstore() nounwind {
; MIPS32: truncstore:
store volatile <4 x i8> <i8 -1, i8 -1, i8 -1, i8 -1>, <4 x i8>*@v4i8
; TODO: What code should be emitted?
ret void
; MIPS32: .size truncstore
}

21
test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll Normal file
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@ -0,0 +1,21 @@
; RUN: llc -march=mips < %s
; RUN: llc -march=mips -mattr=+MSA < %s
; This test originally failed to select code for a truncstore of a
; build_vector.
; It should at least successfully build.
define void @autogen_SD742806235(i8*, i32*, i64*, i32, i64, i8) {
BB:
%A4 = alloca double
%A3 = alloca double
%A2 = alloca <8 x i8>
%A1 = alloca <4 x float>
%A = alloca i1
store i8 %5, i8* %0
store i8 %5, i8* %0
store i8 %5, i8* %0
store <8 x i8> <i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1>, <8 x i8>* %A2
store i8 %5, i8* %0
ret void
}