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Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend

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(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.

We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>.  See, for example, A8.6.57/58/60.

And modified test cases to not expect '+' in +reg or #+num.  For example,

; CHECK:       ldr.w	r9, [r7, #28]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98637 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2010-03-16 16:36:54 +00:00
parent ea7f22c31d
commit d30a98e43a
33 changed files with 9189 additions and 168 deletions
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8
utils/TableGen/TableGen.cpp
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@ -31,6 +31,7 @@
#include "OptParserEmitter.h"
#include "Record.h"
#include "RegisterInfoEmitter.h"
#include "RISCDisassemblerEmitter.h"
#include "SubtargetEmitter.h"
#include "TGParser.h"
#include "llvm/Support/CommandLine.h"
@ -48,6 +49,7 @@ enum ActionType {
GenEmitter,
GenRegisterEnums, GenRegister, GenRegisterHeader,
GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
GenRISCDisassembler,
GenDisassembler,
GenCallingConv,
GenClangDiagsDefs,
@ -84,6 +86,9 @@ namespace {
"Generate calling convention descriptions"),
clEnumValN(GenAsmWriter, "gen-asm-writer",
"Generate assembly writer"),
clEnumValN(GenRISCDisassembler, "gen-risc-disassembler",
"Generate disassembler for fixed instruction"
" length"),
clEnumValN(GenDisassembler, "gen-disassembler",
"Generate disassembler"),
clEnumValN(GenAsmMatcher, "gen-asm-matcher",
@ -229,6 +234,9 @@ int main(int argc, char **argv) {
case GenAsmWriter:
AsmWriterEmitter(Records).run(*Out);
break;
case GenRISCDisassembler:
RISCDisassemblerEmitter(Records).run(*Out);
break;
case GenAsmMatcher:
AsmMatcherEmitter(Records).run(*Out);
break;