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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-08 21:32:39 +00:00
Cosmetic changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103155 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -738,16 +738,16 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
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.addReg(SrcReg, getKillRegState(isKill))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
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.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
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} else if (RC == ARM::SPRRegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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} else if (RC == ARM::DPRRegisterClass ||
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} else if (RC == ARM::DPRRegisterClass ||
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RC == ARM::DPR_VFP2RegisterClass ||
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RC == ARM::DPR_VFP2RegisterClass ||
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RC == ARM::DPR_8RegisterClass) {
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RC == ARM::DPR_8RegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
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.addReg(SrcReg, getKillRegState(isKill))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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} else if (RC == ARM::SPRRegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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} else {
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} else {
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assert((RC == ARM::QPRRegisterClass ||
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assert((RC == ARM::QPRRegisterClass ||
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RC == ARM::QPR_VFP2RegisterClass ||
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RC == ARM::QPR_VFP2RegisterClass ||
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@ -792,14 +792,14 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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if (RC == ARM::GPRRegisterClass) {
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if (RC == ARM::GPRRegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
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.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
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.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
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} else if (RC == ARM::SPRRegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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} else if (RC == ARM::DPRRegisterClass ||
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} else if (RC == ARM::DPRRegisterClass ||
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RC == ARM::DPR_VFP2RegisterClass ||
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RC == ARM::DPR_VFP2RegisterClass ||
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RC == ARM::DPR_8RegisterClass) {
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RC == ARM::DPR_8RegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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} else if (RC == ARM::SPRRegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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} else {
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} else {
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assert((RC == ARM::QPRRegisterClass ||
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assert((RC == ARM::QPRRegisterClass ||
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RC == ARM::QPR_VFP2RegisterClass ||
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RC == ARM::QPR_VFP2RegisterClass ||
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