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Temporarily revert r129408 to see if it brings the bots back.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129417 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2011-04-13 00:20:59 +00:00
parent 066c2f495a
commit d31df87f41
2 changed files with 2 additions and 15 deletions
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2
lib/CodeGen/RegAllocFast.cpp
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@ -442,6 +442,8 @@ unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
unsigned Cost = 0; unsigned Cost = 0;
for (const unsigned *AS = TRI->getAliasSet(PhysReg); for (const unsigned *AS = TRI->getAliasSet(PhysReg);
unsigned Alias = *AS; ++AS) { unsigned Alias = *AS; ++AS) {
if (UsedInInstr.test(Alias))
return spillImpossible;
switch (unsigned VirtReg = PhysRegState[Alias]) { switch (unsigned VirtReg = PhysRegState[Alias]) {
case regDisabled: case regDisabled:
break; break;

15
test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll
View File

@ -1,15 +0,0 @@
; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=fast
; Previously we'd crash as out of registers on this input by clobbering all of
; the aliases.
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
target triple = "thumbv7-apple-darwin10.0.0"
define void @_Z8TestCasev() nounwind ssp {
entry:
%a = alloca float, align 4
%tmp = load float* %a, align 4
call void asm sideeffect "", "w,~{s0},~{s16}"(float %tmp) nounwind, !srcloc !0
ret void
}
!0 = metadata !{i32 109}