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Thumb2 assembly parsing and encoding for MVN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139739 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
34626acf7f
commit
d32872f9ca
@ -458,47 +458,6 @@ class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
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}
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/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
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/// unary operation that produces a value. These are predicable and can be
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/// changed to modify CPSR.
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multiclass T2I_un_irs<bits<4> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
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PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
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// shifted imm
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def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
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opc, "\t$Rd, $imm",
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[(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
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let isAsCheapAsAMove = Cheap;
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let isReMaterializable = ReMat;
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let Inst{31-27} = 0b11110;
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let Inst{25} = 0;
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let Inst{24-21} = opcod;
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let Inst{19-16} = 0b1111; // Rn
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let Inst{15} = 0;
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}
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// register
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def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
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opc, ".w\t$Rd, $Rm",
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[(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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let Inst{19-16} = 0b1111; // Rn
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let Inst{14-12} = 0b000; // imm3
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let Inst{7-6} = 0b00; // imm2
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let Inst{5-4} = 0b00; // type
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}
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// shifted register
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def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
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opc, ".w\t$Rd, $ShiftedRm",
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[(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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let Inst{19-16} = 0b1111; // Rn
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}
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}
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/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
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/// binary operation that produces a value. These are predicable and can be
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/// changed to modify CPSR.
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@ -2247,13 +2206,53 @@ defm t2ORN : T2I_bin_irs<0b0011, "orn",
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BinOpFrag<(or node:$LHS, (not node:$RHS))>,
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"t2ORN", 0, "">;
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/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
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/// unary operation that produces a value. These are predicable and can be
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/// changed to modify CPSR.
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multiclass T2I_un_irs<bits<4> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
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PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
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// shifted imm
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def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
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opc, "\t$Rd, $imm",
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[(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
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let isAsCheapAsAMove = Cheap;
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let isReMaterializable = ReMat;
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let Inst{31-27} = 0b11110;
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let Inst{25} = 0;
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let Inst{24-21} = opcod;
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let Inst{19-16} = 0b1111; // Rn
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let Inst{15} = 0;
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}
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// register
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def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
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opc, ".w\t$Rd, $Rm",
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[(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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let Inst{19-16} = 0b1111; // Rn
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let Inst{14-12} = 0b000; // imm3
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let Inst{7-6} = 0b00; // imm2
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let Inst{5-4} = 0b00; // type
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}
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// shifted register
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def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
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opc, ".w\t$Rd, $ShiftedRm",
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[(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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let Inst{19-16} = 0b1111; // Rn
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}
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}
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// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
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let AddedComplexity = 1 in
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defm t2MVN : T2I_un_irs <0b0011, "mvn",
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IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
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UnOpFrag<(not node:$Src)>, 1, 1>;
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let AddedComplexity = 1 in
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def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
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(t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
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@ -3820,3 +3819,9 @@ def : t2InstAlias<"ldrsb${p} $Rt, $addr",
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(t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
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def : t2InstAlias<"ldrsh${p} $Rt, $addr",
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(t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
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// Alias for MVN without the ".w" optional width specifier.
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def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
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(t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
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def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
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(t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
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@ -1123,6 +1123,51 @@ _func:
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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@ CHECK: muleq r3, r4, r5 @ encoding: [0x04,0xfb,0x05,0xf3]
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@------------------------------------------------------------------------------
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@ MVN(immediate)
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@------------------------------------------------------------------------------
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mvns r8, #21
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mvn r0, #0x3fc0000
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mvns r0, #0x3fc0000
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itte eq
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mvnseq r1, #12
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mvneq r1, #12
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mvnne r1, #12
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@ CHECK: mvns r8, #21 @ encoding: [0x7f,0xf0,0x15,0x08]
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@ CHECK: mvn r0, #66846720 @ encoding: [0x6f,0xf0,0x7f,0x70]
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@ CHECK: mvns r0, #66846720 @ encoding: [0x7f,0xf0,0x7f,0x70]
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@ CHECK: itte eq @ encoding: [0x06,0xbf]
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@ CHECK: mvnseq r1, #12 @ encoding: [0x7f,0xf0,0x0c,0x01]
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@ CHECK: mvneq r1, #12 @ encoding: [0x6f,0xf0,0x0c,0x01]
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@ CHECK: mvnne r1, #12 @ encoding: [0x6f,0xf0,0x0c,0x01]
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@------------------------------------------------------------------------------
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@ MVN(register)
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@------------------------------------------------------------------------------
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mvn r2, r3
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mvns r2, r3
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mvn r5, r6, lsl #19
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mvn r5, r6, lsr #9
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mvn r5, r6, asr #4
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mvn r5, r6, ror #6
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mvn r5, r6, rrx
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it eq
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mvneq r2, r3
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@ CHECK: mvn.w r2, r3 @ encoding: [0x6f,0xea,0x03,0x02]
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@ CHECK: mvns r2, r3 @ encoding: [0xda,0x43]
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@ CHECK: mvn.w r5, r6, lsl #19 @ encoding: [0x6f,0xea,0xc6,0x45]
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@ CHECK: mvn.w r5, r6, lsr #9 @ encoding: [0x6f,0xea,0x56,0x25]
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@ CHECK: mvn.w r5, r6, asr #4 @ encoding: [0x6f,0xea,0x26,0x15]
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@ CHECK: mvn.w r5, r6, ror #6 @ encoding: [0x6f,0xea,0xb6,0x15]
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@ CHECK: mvn.w r5, r6, rrx @ encoding: [0x6f,0xea,0x36,0x05]
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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@ CHECK: mvneq r2, r3 @ encoding: [0xda,0x43]
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@------------------------------------------------------------------------------
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@ IT
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@------------------------------------------------------------------------------
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