From d32872f9ca446fc48084082fcb88255a55405cc2 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 14 Sep 2011 21:24:41 +0000 Subject: [PATCH] Thumb2 assembly parsing and encoding for MVN. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139739 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb2.td | 89 +++++++++++++------------ test/MC/ARM/basic-thumb2-instructions.s | 45 +++++++++++++ 2 files changed, 92 insertions(+), 42 deletions(-) diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 6ef443e9524..6fcb8e0475b 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -458,47 +458,6 @@ class T2MulLong opc22_20, bits<4> opc7_4, } -/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a -/// unary operation that produces a value. These are predicable and can be -/// changed to modify CPSR. -multiclass T2I_un_irs opcod, string opc, - InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, - PatFrag opnode, bit Cheap = 0, bit ReMat = 0> { - // shifted imm - def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii, - opc, "\t$Rd, $imm", - [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> { - let isAsCheapAsAMove = Cheap; - let isReMaterializable = ReMat; - let Inst{31-27} = 0b11110; - let Inst{25} = 0; - let Inst{24-21} = opcod; - let Inst{19-16} = 0b1111; // Rn - let Inst{15} = 0; - } - // register - def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir, - opc, ".w\t$Rd, $Rm", - [(set rGPR:$Rd, (opnode rGPR:$Rm))]> { - let Inst{31-27} = 0b11101; - let Inst{26-25} = 0b01; - let Inst{24-21} = opcod; - let Inst{19-16} = 0b1111; // Rn - let Inst{14-12} = 0b000; // imm3 - let Inst{7-6} = 0b00; // imm2 - let Inst{5-4} = 0b00; // type - } - // shifted register - def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis, - opc, ".w\t$Rd, $ShiftedRm", - [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> { - let Inst{31-27} = 0b11101; - let Inst{26-25} = 0b01; - let Inst{24-21} = opcod; - let Inst{19-16} = 0b1111; // Rn - } -} - /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a /// binary operation that produces a value. These are predicable and can be /// changed to modify CPSR. @@ -2247,13 +2206,53 @@ defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>, "t2ORN", 0, "">; +/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a +/// unary operation that produces a value. These are predicable and can be +/// changed to modify CPSR. +multiclass T2I_un_irs opcod, string opc, + InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, + PatFrag opnode, bit Cheap = 0, bit ReMat = 0> { + // shifted imm + def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii, + opc, "\t$Rd, $imm", + [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> { + let isAsCheapAsAMove = Cheap; + let isReMaterializable = ReMat; + let Inst{31-27} = 0b11110; + let Inst{25} = 0; + let Inst{24-21} = opcod; + let Inst{19-16} = 0b1111; // Rn + let Inst{15} = 0; + } + // register + def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir, + opc, ".w\t$Rd, $Rm", + [(set rGPR:$Rd, (opnode rGPR:$Rm))]> { + let Inst{31-27} = 0b11101; + let Inst{26-25} = 0b01; + let Inst{24-21} = opcod; + let Inst{19-16} = 0b1111; // Rn + let Inst{14-12} = 0b000; // imm3 + let Inst{7-6} = 0b00; // imm2 + let Inst{5-4} = 0b00; // type + } + // shifted register + def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis, + opc, ".w\t$Rd, $ShiftedRm", + [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> { + let Inst{31-27} = 0b11101; + let Inst{26-25} = 0b01; + let Inst{24-21} = opcod; + let Inst{19-16} = 0b1111; // Rn + } +} + // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version let AddedComplexity = 1 in defm t2MVN : T2I_un_irs <0b0011, "mvn", IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi, UnOpFrag<(not node:$Src)>, 1, 1>; - let AddedComplexity = 1 in def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm), (t2BICri rGPR:$src, t2_so_imm_not:$imm)>; @@ -3820,3 +3819,9 @@ def : t2InstAlias<"ldrsb${p} $Rt, $addr", (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; def : t2InstAlias<"ldrsh${p} $Rt, $addr", (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; + +// Alias for MVN without the ".w" optional width specifier. +def : t2InstAlias<"mvn${s}${p} $Rd, $Rm", + (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>; +def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm", + (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>; diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index cca547d673b..98ec7f3643d 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -1123,6 +1123,51 @@ _func: @ CHECK: it eq @ encoding: [0x08,0xbf] @ CHECK: muleq r3, r4, r5 @ encoding: [0x04,0xfb,0x05,0xf3] + +@------------------------------------------------------------------------------ +@ MVN(immediate) +@------------------------------------------------------------------------------ + mvns r8, #21 + mvn r0, #0x3fc0000 + mvns r0, #0x3fc0000 + itte eq + mvnseq r1, #12 + mvneq r1, #12 + mvnne r1, #12 + +@ CHECK: mvns r8, #21 @ encoding: [0x7f,0xf0,0x15,0x08] +@ CHECK: mvn r0, #66846720 @ encoding: [0x6f,0xf0,0x7f,0x70] +@ CHECK: mvns r0, #66846720 @ encoding: [0x7f,0xf0,0x7f,0x70] +@ CHECK: itte eq @ encoding: [0x06,0xbf] +@ CHECK: mvnseq r1, #12 @ encoding: [0x7f,0xf0,0x0c,0x01] +@ CHECK: mvneq r1, #12 @ encoding: [0x6f,0xf0,0x0c,0x01] +@ CHECK: mvnne r1, #12 @ encoding: [0x6f,0xf0,0x0c,0x01] + + +@------------------------------------------------------------------------------ +@ MVN(register) +@------------------------------------------------------------------------------ + mvn r2, r3 + mvns r2, r3 + mvn r5, r6, lsl #19 + mvn r5, r6, lsr #9 + mvn r5, r6, asr #4 + mvn r5, r6, ror #6 + mvn r5, r6, rrx + it eq + mvneq r2, r3 + +@ CHECK: mvn.w r2, r3 @ encoding: [0x6f,0xea,0x03,0x02] +@ CHECK: mvns r2, r3 @ encoding: [0xda,0x43] +@ CHECK: mvn.w r5, r6, lsl #19 @ encoding: [0x6f,0xea,0xc6,0x45] +@ CHECK: mvn.w r5, r6, lsr #9 @ encoding: [0x6f,0xea,0x56,0x25] +@ CHECK: mvn.w r5, r6, asr #4 @ encoding: [0x6f,0xea,0x26,0x15] +@ CHECK: mvn.w r5, r6, ror #6 @ encoding: [0x6f,0xea,0xb6,0x15] +@ CHECK: mvn.w r5, r6, rrx @ encoding: [0x6f,0xea,0x36,0x05] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: mvneq r2, r3 @ encoding: [0xda,0x43] + + @------------------------------------------------------------------------------ @ IT @------------------------------------------------------------------------------