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Fixes an assertion failure while disassembling ARM rsbs reg/reg form.
Patch by Ted Kremenek! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126895 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2203,6 +2203,19 @@ def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
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let Inst{19-16} = Rn;
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let Inst{11-0} = imm;
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}
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def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
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IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
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[/* For disassembly only; pattern left blank */]> {
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bits<4> Rd;
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bits<4> Rn;
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bits<4> Rm;
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let Inst{11-4} = 0b00000000;
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let Inst{25} = 0;
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let Inst{20} = 1;
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let Inst{3-0} = Rm;
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let Inst{15-12} = Rd;
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let Inst{19-16} = Rn;
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}
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def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
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DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
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[(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
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@ -130,3 +130,6 @@
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# CHECK: msr cpsr_fc, r0
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0x00 0xf0 0x29 0xe1
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# CHECK: rsbs r6, r7, r8
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0x08 0x60 0x77 0xe0
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