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ARM: Permit "sp" in ARM variant of STREXD instructions

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Patch from Mihail Popa

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179854 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2013-04-19 15:44:32 +00:00
parent 143d223447
commit d3af696c08
2 changed files with 3 additions and 2 deletions
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2
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -3573,7 +3573,7 @@ static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
unsigned Rn = fieldFromInstruction(Insn, 16, 4);
unsigned pred = fieldFromInstruction(Insn, 28, 4);
if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;

3
test/MC/Disassembler/ARM/basic-arm-instructions.txt
View File

@ -1823,12 +1823,13 @@
# CHECK: strexh r4, r2, [r5
# CHECK: strex r2, r1, [r7
# CHECK: strexd r6, r2, r3, [r8
# CHECK: strexd sp, r0, r1, [r0]
0x93 0x1f 0xc4 0xe1
0x92 0x4f 0xe5 0xe1
0x91 0x2f 0x87 0xe1
0x92 0x6f 0xa8 0xe1
0x90 0xdf 0xa0 0xe1
#------------------------------------------------------------------------------
# SUB