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Remove references to INSERT_SUBREG after de-SSA

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107732 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-07-06 23:40:35 +00:00
parent d491d6ecd2
commit d3b376b448
7 changed files with 9 additions and 136 deletions
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6
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -324,12 +324,6 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
if (mi->isCopyLike() ||
tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
CopyMI = mi;
// Some of the REG_SEQUENCE lowering in TwoAddressInstrPass creates
// implicit defs without really knowing. It shows up as INSERT_SUBREG
// using an undefined register.
if (mi->isInsertSubreg())
mi->getOperand(1).setIsUndef();
}
VNInfo *ValNo = interval.getNextValue(defIndex, CopyMI, true,

88
lib/CodeGen/LowerSubregs.cpp
View File

@ -54,7 +54,6 @@ namespace {
private:
bool LowerExtract(MachineInstr *MI);
bool LowerInsert(MachineInstr *MI);
bool LowerSubregToReg(MachineInstr *MI);
bool LowerCopy(MachineInstr *MI);
@ -238,90 +237,6 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
return true;
}
bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent();
assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
(MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
(MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
MI->getOperand(3).isImm() && "Invalid insert_subreg");
unsigned DstReg = MI->getOperand(0).getReg();
#ifndef NDEBUG
unsigned SrcReg = MI->getOperand(1).getReg();
#endif
unsigned InsReg = MI->getOperand(2).getReg();
unsigned SubIdx = MI->getOperand(3).getImm();
assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
assert(SubIdx != 0 && "Invalid index for insert_subreg");
unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
assert(DstSubReg && "invalid subregister index for register");
assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
"Insert superreg source must be in a physical register");
assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
"Inserted value must be in a physical register");
DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
if (DstSubReg == InsReg) {
// No need to insert an identity copy instruction. If the SrcReg was
// <undef>, we need to make sure it is alive by inserting a KILL
if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
TII->get(TargetOpcode::KILL), DstReg);
if (MI->getOperand(2).isUndef())
MIB.addReg(InsReg, RegState::Undef);
else
MIB.addReg(InsReg, RegState::Kill);
} else {
DEBUG(dbgs() << "subreg: eliminated!\n");
MBB->erase(MI);
return true;
}
} else {
// Insert sub-register copy
const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
if (MI->getOperand(2).isUndef())
// If the source register being inserted is undef, then this becomes a
// KILL.
BuildMI(*MBB, MI, MI->getDebugLoc(),
TII->get(TargetOpcode::KILL), DstSubReg);
else {
bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1,
MI->getDebugLoc());
(void)Emitted;
assert(Emitted && "Subreg and Dst must be of compatible register class");
}
MachineBasicBlock::iterator CopyMI = MI;
--CopyMI;
// INSERT_SUBREG is a two-address instruction so it implicitly kills SrcReg.
if (!MI->getOperand(1).isUndef())
CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
// Transfer the kill/dead flags, if needed.
if (MI->getOperand(0).isDead()) {
TransferDeadFlag(MI, DstSubReg, TRI);
} else {
// Make sure the full DstReg is live after this replacement.
CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true));
}
// Make sure the inserted register gets killed
if (MI->getOperand(2).isKill() && !MI->getOperand(2).isUndef())
TransferKillFlag(MI, InsReg, TRI);
}
DEBUG({
MachineBasicBlock::iterator dMI = MI;
dbgs() << "subreg: " << *(--dMI) << "\n";
});
MBB->erase(MI);
return true;
}
bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
MachineOperand &DstMO = MI->getOperand(0);
MachineOperand &SrcMO = MI->getOperand(1);
@ -387,10 +302,9 @@ bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
mi != me;) {
MachineBasicBlock::iterator nmi = llvm::next(mi);
MachineInstr *MI = mi;
assert(!MI->isInsertSubreg() && "INSERT_SUBREG should no longer appear");
if (MI->isExtractSubreg()) {
MadeChange |= LowerExtract(MI);
} else if (MI->isInsertSubreg()) {
MadeChange |= LowerInsert(MI);
} else if (MI->isSubregToReg()) {
MadeChange |= LowerSubregToReg(MI);
} else if (MI->isCopy()) {

15
lib/CodeGen/ProcessImplicitDefs.cpp
View File

@ -102,21 +102,6 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
continue;
}
if (MI->isInsertSubreg()) {
MachineOperand &MO = MI->getOperand(2);
if (ImpDefRegs.count(MO.getReg())) {
// %reg1032<def> = INSERT_SUBREG %reg1032, undef, 2
// This is an identity copy, eliminate it now.
if (MO.isKill()) {
LiveVariables::VarInfo& vi = lv_->getVarInfo(MO.getReg());
vi.removeKill(MI);
}
MI->eraseFromParent();
Changed = true;
continue;
}
}
// Eliminate %reg1032:sub<def> = COPY undef.
if (MI->isCopy() && MI->getOperand(0).getSubReg()) {
MachineOperand &MO = MI->getOperand(1);

2
lib/CodeGen/RegisterCoalescer.cpp
View File

@ -54,7 +54,7 @@ bool CoalescerPair::isMoveInstr(const MachineInstr *MI,
DstSub = MI->getOperand(0).getSubReg();
Src = MI->getOperand(1).getReg();
SrcSub = compose(MI->getOperand(1).getSubReg(), MI->getOperand(2).getImm());
} else if (MI->isInsertSubreg() || MI->isSubregToReg()) {
} else if (MI->isSubregToReg()) {
Dst = MI->getOperand(0).getReg();
DstSub = compose(MI->getOperand(0).getSubReg(), MI->getOperand(3).getImm());
Src = MI->getOperand(2).getReg();

7
lib/CodeGen/SimpleRegisterCoalescing.cpp
View File

@ -1523,12 +1523,7 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
if (Inst->isCopy() || Inst->isExtractSubreg()) {
DstReg = Inst->getOperand(0).getReg();
SrcReg = Inst->getOperand(1).getReg();
} else if (Inst->isInsertSubreg()) {
DstReg = Inst->getOperand(0).getReg();
SrcReg = Inst->getOperand(2).getReg();
if (Inst->getOperand(1).isUndef())
isInsUndef = true;
} else if (Inst->isInsertSubreg() || Inst->isSubregToReg()) {
} else if (Inst->isSubregToReg()) {
DstReg = Inst->getOperand(0).getReg();
SrcReg = Inst->getOperand(2).getReg();
} else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))

3
lib/CodeGen/StackSlotColoring.cpp
View File

@ -508,8 +508,7 @@ bool StackSlotColoring::PropagateBackward(MachineBasicBlock::iterator MII,
// Abort the use is actually a sub-register def. We don't have enough
// information to figure out if it is really legal.
if (MO.getSubReg() || MII->isExtractSubreg() ||
MII->isInsertSubreg() || MII->isSubregToReg())
if (MO.getSubReg() || MII->isExtractSubreg() || MII->isSubregToReg())
return false;
const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);

24
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -1359,25 +1359,11 @@ TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs,
// Insert a copy or an extract to replace the original extracts.
MachineBasicBlock::iterator InsertLoc = SomeMI;
if (NewSrcSubIdx) {
// Insert an extract subreg.
BuildMI(*SomeMI->getParent(), InsertLoc, SomeMI->getDebugLoc(),
TII->get(TargetOpcode::EXTRACT_SUBREG), DstReg)
.addReg(SrcReg).addImm(NewSrcSubIdx);
} else if (NewDstSubIdx) {
// Do a subreg insertion.
BuildMI(*SomeMI->getParent(), InsertLoc, SomeMI->getDebugLoc(),
TII->get(TargetOpcode::INSERT_SUBREG), DstReg)
.addReg(DstReg).addReg(SrcReg).addImm(NewDstSubIdx);
} else {
// Insert a copy.
bool Emitted =
TII->copyRegToReg(*SomeMI->getParent(), InsertLoc, DstReg, SrcReg,
MRI->getRegClass(DstReg), MRI->getRegClass(SrcReg),
SomeMI->getDebugLoc());
(void)Emitted;
}
MachineBasicBlock::iterator CopyMI = prior(InsertLoc);
MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI,
SomeMI->getDebugLoc(),
TII->get(TargetOpcode::COPY))
.addReg(DstReg, RegState::Define, NewDstSubIdx)
.addReg(SrcReg, 0, NewSrcSubIdx);
// Remove all the old extract instructions.
for (MachineRegisterInfo::use_nodbg_iterator