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Enable post-alloc scheduling for all ARM variants except for Thumb1.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84249 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-10-16 06:11:08 +00:00
parent c83da2f9e3
commit d3dd50fec0
2 changed files with 10 additions and 8 deletions
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8
lib/Target/ARM/ARMSubtarget.cpp
View File

@ -27,11 +27,11 @@ UseNEONFP("arm-use-neon-fp",
cl::init(false), cl::Hidden); cl::init(false), cl::Hidden);
ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS, ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
bool isThumb) bool isT)
: ARMArchVersion(V4T) : ARMArchVersion(V4T)
, ARMFPUType(None) , ARMFPUType(None)
, UseNEONForSinglePrecisionFP(UseNEONFP) , UseNEONForSinglePrecisionFP(UseNEONFP)
, IsThumb(isThumb) , IsThumb(isT)
, ThumbMode(Thumb1) , ThumbMode(Thumb1)
, PostRAScheduler(false) , PostRAScheduler(false)
, IsR9Reserved(ReserveR9) , IsR9Reserved(ReserveR9)
@ -98,9 +98,11 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
if (isTargetDarwin()) if (isTargetDarwin())
IsR9Reserved = ReserveR9 | (ARMArchVersion < V6); IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
if (!isThumb() || hasThumb2())
PostRAScheduler = true;
// Set CPU specific features. // Set CPU specific features.
if (CPUString == "cortex-a8") { if (CPUString == "cortex-a8") {
PostRAScheduler = true;
// On Cortext-a8, it's faster to perform some single-precision FP // On Cortext-a8, it's faster to perform some single-precision FP
// operations with NEON instructions. // operations with NEON instructions.
if (UseNEONFP.getPosition() == 0) if (UseNEONFP.getPosition() == 0)

4
test/CodeGen/ARM/ldrd.ll
View File

@ -10,10 +10,10 @@ entry:
;V6: ldrd r2, [r2] ;V6: ldrd r2, [r2]
;V5: ldr r3, [r2] ;V5: ldr r3, [r2]
;V5-NEXT: ldr r2, [r2, #+4] ;V5: ldr r2, [r2, #+4]
;EABI: ldr r3, [r2] ;EABI: ldr r3, [r2]
;EABI-NEXT: ldr r2, [r2, #+4] ;EABI: ldr r2, [r2, #+4]
%0 = load i64** @b, align 4 %0 = load i64** @b, align 4
%1 = load i64* %0, align 4 %1 = load i64* %0, align 4