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https://github.com/c64scene-ar/llvm-6502.git
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Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121798 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -123,6 +123,8 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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return Value;
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return Value;
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}
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}
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case ARM::fixup_thumb_adr_pcrel_10:
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return ((Value - 4) >> 2) & 0xff;
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case ARM::fixup_arm_adr_pcrel_12: {
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case ARM::fixup_arm_adr_pcrel_12: {
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// ARM PC-relative values are offset by 8.
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// ARM PC-relative values are offset by 8.
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Value -= 8;
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Value -= 8;
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@@ -358,6 +360,7 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
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case ARM::fixup_arm_thumb_bcc:
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case ARM::fixup_arm_thumb_bcc:
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case ARM::fixup_arm_thumb_cp:
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case ARM::fixup_arm_thumb_cp:
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case ARM::fixup_thumb_adr_pcrel_10:
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return 1;
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return 1;
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case ARM::fixup_arm_thumb_br:
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case ARM::fixup_arm_thumb_br:
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@@ -747,11 +747,13 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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return;
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return;
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}
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}
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case ARM::LEApcrel:
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case ARM::LEApcrel:
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case ARM::tLEApcrel:
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case ARM::t2LEApcrel: {
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case ARM::t2LEApcrel: {
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// FIXME: Need to also handle globals and externals
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// FIXME: Need to also handle globals and externals
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MCInst TmpInst;
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MCInst TmpInst;
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TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel
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TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
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? ARM::t2ADR : ARM::ADR);
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: (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
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: ARM::ADR));
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populateADROperands(TmpInst, MI->getOperand(0).getReg(),
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populateADROperands(TmpInst, MI->getOperand(0).getReg(),
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GetCPISymbol(MI->getOperand(1).getIndex()),
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GetCPISymbol(MI->getOperand(1).getIndex()),
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MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
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MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
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@@ -759,11 +761,13 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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OutStreamer.EmitInstruction(TmpInst);
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OutStreamer.EmitInstruction(TmpInst);
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return;
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return;
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}
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}
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case ARM::t2LEApcrelJT:
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case ARM::LEApcrelJT:
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case ARM::LEApcrelJT: {
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case ARM::tLEApcrelJT:
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case ARM::t2LEApcrelJT: {
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MCInst TmpInst;
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MCInst TmpInst;
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TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT
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TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
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? ARM::t2ADR : ARM::ADR);
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: (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
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: ARM::ADR));
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populateADROperands(TmpInst, MI->getOperand(0).getReg(),
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populateADROperands(TmpInst, MI->getOperand(0).getReg(),
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GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
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GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
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MI->getOperand(2).getImm()),
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MI->getOperand(2).getImm()),
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@@ -171,6 +171,8 @@ namespace {
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const { return 0; }
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const { return 0; }
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unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
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unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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const { return 0; }
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unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
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unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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const { return 0; }
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unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
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unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
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@@ -30,6 +30,10 @@ enum Fixups {
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// fixup_t2_pcrel_10 - Equivalent to fixup_arm_pcrel_10, accounting for
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// fixup_t2_pcrel_10 - Equivalent to fixup_arm_pcrel_10, accounting for
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// the short-swapped encoding of Thumb2 instructions.
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// the short-swapped encoding of Thumb2 instructions.
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fixup_t2_pcrel_10,
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fixup_t2_pcrel_10,
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// fixup_thumb_adr_pcrel_10 - 10-bit PC relative relocation for symbol
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// addresses where the lower 2 bits are not encoded (so it's encoded as an
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// 8-bit immediate).
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fixup_thumb_adr_pcrel_10,
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// fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
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// fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
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// instruction.
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// instruction.
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fixup_arm_adr_pcrel_12,
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fixup_arm_adr_pcrel_12,
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@@ -67,6 +67,11 @@ def thumb_immshifted_shamt : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(V, MVT::i32);
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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}]>;
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// ADR instruction labels.
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def t_adrlabel : Operand<i32> {
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let EncoderMethod = "getThumbAdrLabelOpValue";
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}
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// Scaled 4 immediate.
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// Scaled 4 immediate.
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def t_imm_s4 : Operand<i32> {
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def t_imm_s4 : Operand<i32> {
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let PrintMethod = "printThumbS4ImmOperand";
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let PrintMethod = "printThumbS4ImmOperand";
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@@ -1303,25 +1308,23 @@ def tMOVCCi : T1pIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$Rm), IIC_iCMOVi,
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// tLEApcrel - Load a pc-relative address into a register without offending the
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// tLEApcrel - Load a pc-relative address into a register without offending the
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// assembler.
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// assembler.
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let neverHasSideEffects = 1, isReMaterializable = 1 in
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def tLEApcrel : T1I<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), IIC_iALUi,
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def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
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"adr${p}\t$Rd, #$label", []>,
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IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
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T1Encoding<{1,0,1,0,0,?}> {
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T1Encoding<{1,0,1,0,0,?}> {
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// A6.2 & A8.6.10
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bits<3> Rd;
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bits<3> Rd;
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bits<8> addr;
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let Inst{10-8} = Rd;
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let Inst{10-8} = Rd;
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// FIXME: Add label encoding/fixup
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let Inst{7-0} = addr;
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}
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}
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def tLEApcrelJT : T1I<(outs tGPR:$Rd),
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let neverHasSideEffects = 1, isReMaterializable = 1 in
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(ins i32imm:$label, nohash_imm:$id, pred:$p),
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def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
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IIC_iALUi, "adr${p}\t$Rd, #${label}_${id}", []>,
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Size2Bytes, IIC_iALUi, []>;
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T1Encoding<{1,0,1,0,0,?}> {
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// A6.2 & A8.6.10
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def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
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bits<3> Rd;
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(ins i32imm:$label, nohash_imm:$id, pred:$p),
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let Inst{10-8} = Rd;
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Size2Bytes, IIC_iALUi, []>;
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// FIXME: Add label encoding/fixup
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// TLS Instructions
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// TLS Instructions
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@@ -55,6 +55,7 @@ public:
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{ "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
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{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
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MCFixupKindInfo::FKF_IsAligned},
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MCFixupKindInfo::FKF_IsAligned},
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{ "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
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{ "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
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MCFixupKindInfo::FKF_IsAligned},
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MCFixupKindInfo::FKF_IsAligned},
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@@ -135,6 +136,8 @@ public:
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/// ADR label target.
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/// ADR label target.
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uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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SmallVectorImpl<MCFixup> &Fixups) const;
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uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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SmallVectorImpl<MCFixup> &Fixups) const;
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@@ -559,6 +562,16 @@ getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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Fixups);
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Fixups);
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}
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}
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/// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
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/// target.
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uint32_t ARMMCCodeEmitter::
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getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
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return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
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Fixups);
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}
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/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
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/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
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/// operand.
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/// operand.
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uint32_t ARMMCCodeEmitter::
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uint32_t ARMMCCodeEmitter::
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@@ -1679,12 +1679,8 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
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if (Name == "tTPsoft" || Name == "t2TPsoft")
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if (Name == "tTPsoft" || Name == "t2TPsoft")
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return false;
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return false;
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// Ignore tLEApcrel and tLEApcrelJT, prefer tADDrPCi.
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// Ignore tADR, prefer tADDrPCi.
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if (Name == "tLEApcrel" || Name == "tLEApcrelJT")
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if (Name == "tADR")
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return false;
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// Ignore t2LEApcrel, prefer the generic t2ADD* for disassembly printing.
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if (Name == "t2LEApcrel")
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return false;
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return false;
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// Ignore tADDrSP, tADDspr, and tPICADD, prefer the generic tADDhirr.
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// Ignore tADDrSP, tADDspr, and tPICADD, prefer the generic tADDhirr.
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@@ -1711,13 +1707,12 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
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// tSpill conflicts with tSTRspi
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// tSpill conflicts with tSTRspi
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// tLDRcp conflicts with tLDRspi
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// tLDRcp conflicts with tLDRspi
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// tRestore conflicts with tLDRspi
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// tRestore conflicts with tLDRspi
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// t2LEApcrelJT conflicts with t2LEApcrel
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// t2MOVCCi16 conflicts with tMOVi16
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// t2MOVCCi16 conflicts with tMOVi16
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if (Name == "tBfar" ||
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if (Name == "tBfar" ||
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Name == "tPOP_RET" || Name == "t2LDMIA_RET" ||
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Name == "tPOP_RET" || Name == "t2LDMIA_RET" ||
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Name == "tMOVCCi" || Name == "tMOVCCr" ||
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Name == "tMOVCCi" || Name == "tMOVCCr" ||
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Name == "tSpill" || Name == "tLDRcp" || Name == "tRestore" ||
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Name == "tSpill" || Name == "tLDRcp" || Name == "tRestore" ||
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Name == "t2LEApcrelJT" || Name == "t2MOVCCi16")
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Name == "t2MOVCCi16")
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return false;
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return false;
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}
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}
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@@ -584,6 +584,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
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IMM("t_imm_s4");
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IMM("t_imm_s4");
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IMM("pclabel");
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IMM("pclabel");
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IMM("adrlabel");
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IMM("adrlabel");
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IMM("t_adrlabel");
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IMM("t2adrlabel");
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IMM("t2adrlabel");
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IMM("shift_imm");
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IMM("shift_imm");
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IMM("neon_vcvt_imm32");
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IMM("neon_vcvt_imm32");
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