mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-02 07:11:49 +00:00
[MachineSink] Use the real post dominator tree
Summary: Fixes a FIXME in MachineSinking. Instead of using the simple heuristics in isPostDominatedBy, use the real MachinePostDominatorTree. The old heuristics caused instructions to sink unnecessarily, and might create register pressure. Test Plan: Added a NVPTX codegen test to verify that our change is in effect. It also shows the unnecessary register pressure caused by over-sinking. Updated affected tests in AArch64 and X86. Reviewers: eliben, meheff, Jiangning Reviewed By: Jiangning Subscribers: jholewinski, aemerson, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D4814 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216862 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jingyue Wu
parent
e2cf6dc5c9
commit
d43e6df10b
@ -23,6 +23,7 @@
|
||||
#include "llvm/Analysis/AliasAnalysis.h"
|
||||
#include "llvm/CodeGen/MachineDominators.h"
|
||||
#include "llvm/CodeGen/MachineLoopInfo.h"
|
||||
#include "llvm/CodeGen/MachinePostDominators.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
@ -48,8 +49,9 @@ namespace {
|
||||
class MachineSinking : public MachineFunctionPass {
|
||||
const TargetInstrInfo *TII;
|
||||
const TargetRegisterInfo *TRI;
|
||||
MachineRegisterInfo *MRI; // Machine register information
|
||||
MachineDominatorTree *DT; // Machine dominator tree
|
||||
MachineRegisterInfo *MRI; // Machine register information
|
||||
MachineDominatorTree *DT; // Machine dominator tree
|
||||
MachinePostDominatorTree *PDT; // Machine post dominator tree
|
||||
MachineLoopInfo *LI;
|
||||
AliasAnalysis *AA;
|
||||
|
||||
@ -74,8 +76,10 @@ namespace {
|
||||
MachineFunctionPass::getAnalysisUsage(AU);
|
||||
AU.addRequired<AliasAnalysis>();
|
||||
AU.addRequired<MachineDominatorTree>();
|
||||
AU.addRequired<MachinePostDominatorTree>();
|
||||
AU.addRequired<MachineLoopInfo>();
|
||||
AU.addPreserved<MachineDominatorTree>();
|
||||
AU.addPreserved<MachinePostDominatorTree>();
|
||||
AU.addPreserved<MachineLoopInfo>();
|
||||
}
|
||||
|
||||
@ -236,6 +240,7 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
|
||||
TRI = TM.getSubtargetImpl()->getRegisterInfo();
|
||||
MRI = &MF.getRegInfo();
|
||||
DT = &getAnalysis<MachineDominatorTree>();
|
||||
PDT = &getAnalysis<MachinePostDominatorTree>();
|
||||
LI = &getAnalysis<MachineLoopInfo>();
|
||||
AA = &getAnalysis<AliasAnalysis>();
|
||||
|
||||
@ -453,23 +458,6 @@ static void collectDebugValues(MachineInstr *MI,
|
||||
}
|
||||
}
|
||||
|
||||
/// isPostDominatedBy - Return true if A is post dominated by B.
|
||||
static bool isPostDominatedBy(MachineBasicBlock *A, MachineBasicBlock *B) {
|
||||
|
||||
// FIXME - Use real post dominator.
|
||||
if (A->succ_size() != 2)
|
||||
return false;
|
||||
MachineBasicBlock::succ_iterator I = A->succ_begin();
|
||||
if (B == *I)
|
||||
++I;
|
||||
MachineBasicBlock *OtherSuccBlock = *I;
|
||||
if (OtherSuccBlock->succ_size() != 1 ||
|
||||
*(OtherSuccBlock->succ_begin()) != B)
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/// isProfitableToSinkTo - Return true if it is profitable to sink MI.
|
||||
bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
|
||||
MachineBasicBlock *MBB,
|
||||
@ -481,8 +469,8 @@ bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
|
||||
return false;
|
||||
|
||||
// It is profitable if SuccToSinkTo does not post dominate current block.
|
||||
if (!isPostDominatedBy(MBB, SuccToSinkTo))
|
||||
return true;
|
||||
if (!PDT->dominates(SuccToSinkTo, MBB))
|
||||
return true;
|
||||
|
||||
// Check if only use in post dominated block is PHI instruction.
|
||||
bool NonPHIUse = false;
|
||||
|
||||
@ -47,13 +47,13 @@ define i32 @fetch_and_nand(i32* %p) {
|
||||
|
||||
define i64 @fetch_and_nand_64(i64* %p) {
|
||||
; CHECK-LABEL: fetch_and_nand_64:
|
||||
; CHECK: mov x[[ADDR:[0-9]+]], x0
|
||||
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
|
||||
; CHECK: ldaxr x[[DEST_REG:[0-9]+]], [x[[ADDR]]]
|
||||
; CHECK: ldaxr x[[DEST_REG:[0-9]+]], [x0]
|
||||
; CHECK: mvn w[[TMP_REG:[0-9]+]], w[[DEST_REG]]
|
||||
; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], x[[TMP_REG]], #0xfffffffffffffff8
|
||||
; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
|
||||
; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
|
||||
; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
|
||||
; CHECK: mov x0, x[[DEST_REG]]
|
||||
|
||||
%val = atomicrmw nand i64* %p, i64 7 acq_rel
|
||||
ret i64 %val
|
||||
@ -75,12 +75,12 @@ define i32 @fetch_and_or(i32* %p) {
|
||||
|
||||
define i64 @fetch_and_or_64(i64* %p) {
|
||||
; CHECK: fetch_and_or_64:
|
||||
; CHECK: mov x[[ADDR:[0-9]+]], x0
|
||||
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
|
||||
; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x[[ADDR]]]
|
||||
; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x0]
|
||||
; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], [[DEST_REG]], #0x7
|
||||
; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
|
||||
; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
|
||||
; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
|
||||
; CHECK: mov x0, [[DEST_REG]]
|
||||
%val = atomicrmw or i64* %p, i64 7 monotonic
|
||||
ret i64 %val
|
||||
}
|
||||
|
||||
40
test/CodeGen/NVPTX/machine-sink.ll
Normal file
40
test/CodeGen/NVPTX/machine-sink.ll
Normal file
@ -0,0 +1,40 @@
|
||||
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
|
||||
|
||||
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
|
||||
|
||||
@scalar1 = internal addrspace(3) global float 0.000000e+00, align 4
|
||||
@scalar2 = internal addrspace(3) global float 0.000000e+00, align 4
|
||||
|
||||
; We shouldn't sink mul.rn.f32 to BB %merge because BB %merge post-dominates
|
||||
; BB %entry. Over-sinking created more register pressure on this example. The
|
||||
; backend would sink the fmuls to BB %merge, but not the loads for being
|
||||
; conservative on sinking memory accesses. As a result, the loads and
|
||||
; the two fmuls would be separated to two basic blocks, causing two
|
||||
; cross-BB live ranges.
|
||||
define float @post_dominate(float %x, i1 %cond) {
|
||||
; CHECK-LABEL: post_dominate(
|
||||
entry:
|
||||
%0 = load float* addrspacecast (float addrspace(3)* @scalar1 to float*), align 4
|
||||
%1 = load float* addrspacecast (float addrspace(3)* @scalar2 to float*), align 4
|
||||
; CHECK: ld.shared.f32
|
||||
; CHECK: ld.shared.f32
|
||||
%2 = fmul float %0, %0
|
||||
%3 = fmul float %1, %2
|
||||
; CHECK-NOT: bra
|
||||
; CHECK: mul.rn.f32
|
||||
; CHECK: mul.rn.f32
|
||||
br i1 %cond, label %then, label %merge
|
||||
|
||||
then:
|
||||
%z = fadd float %x, %x
|
||||
br label %then2
|
||||
|
||||
then2:
|
||||
%z2 = fadd float %z, %z
|
||||
br label %merge
|
||||
|
||||
merge:
|
||||
%y = phi float [ 0.0, %entry ], [ %z2, %then2 ]
|
||||
%w = fadd float %y, %3
|
||||
ret float %w
|
||||
}
|
||||
@ -1,6 +1,9 @@
|
||||
; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
|
||||
|
||||
; CHECK: leal 16(%eax), %edx
|
||||
; FIXME: The first two instructions, movl and addl, should have been combined to
|
||||
; "leal 16(%eax), %edx" by the backend (PR20766).
|
||||
; CHECK: movl %eax, %edx
|
||||
; CHECK: addl $16, %edx
|
||||
; CHECK: align
|
||||
; CHECK: addl $4, %edx
|
||||
; CHECK: decl %ecx
|
||||
|
||||
Loading…
Reference in New Issue
Block a user