6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-11-02 22:23:10 +00:00
Code Issues Projects Releases Wiki Activity

[FastISel][AArch64] Use the zero register for stores.

Browse Source 
Use the zero register directly when possible to avoid an unnecessary register
copy and a wasted register at -O0. This also uses integer stores to store a
positive floating-point zero. This saves us from materializing the positive zero
in a register and then storing it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216617 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
2014-08-27 21:04:52 +00:00
parent 305938e272
commit d445e4acdb
3 changed files with 34 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
test/CodeGen/AArch64/arm64-fast-isel.ll
View File

@@ -66,8 +66,7 @@ entry:
define void @t4(i32 *%ptr) nounwind {
entry:
; CHECK-LABEL: t4:
; CHECK: mov w8, wzr
; CHECK: stur w8, [x0, #-4]
; CHECK: stur wzr, [x0, #-4]
; CHECK: ret
%0 = getelementptr i32 *%ptr, i32 -1
store i32 0, i32* %0, align 4
@@ -77,8 +76,7 @@ entry:
define void @t5(i32 *%ptr) nounwind {
entry:
; CHECK-LABEL: t5:
; CHECK: mov w8, wzr
; CHECK: stur w8, [x0, #-256]
; CHECK: stur wzr, [x0, #-256]
; CHECK: ret
%0 = getelementptr i32 *%ptr, i32 -64
store i32 0, i32* %0, align 4

19
test/CodeGen/AArch64/fast-isel-addressing-modes.ll
View File

@@ -1,5 +1,5 @@
; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
; RUN: llc -mtriple=aarch64-apple-darwin -O0 -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
; Load / Store Base Register only
define zeroext i1 @load_breg_i1(i1* %a) {
@@ -53,11 +53,18 @@ define double @load_breg_f64(double* %a) {
define void @store_breg_i1(i1* %a) {
; CHECK-LABEL: store_breg_i1
; CHECK: strb {{wzr|w[0-9]+}}, [x0]
; CHECK: strb wzr, [x0]
store i1 0, i1* %a
ret void
}
define void @store_breg_i1_2(i1* %a) {
; CHECK-LABEL: store_breg_i1_2
; CHECK: strb {{w[0-9]+}}, [x0]
store i1 true, i1* %a
ret void
}
define void @store_breg_i8(i8* %a) {
; CHECK-LABEL: store_breg_i8
; CHECK: strb wzr, [x0]
@@ -88,14 +95,14 @@ define void @store_breg_i64(i64* %a) {
define void @store_breg_f32(float* %a) {
; CHECK-LABEL: store_breg_f32
; CHECK: str {{wzr|s[0-9]+}}, [x0]
; CHECK: str wzr, [x0]
store float 0.0, float* %a
ret void
}
define void @store_breg_f64(double* %a) {
; CHECK-LABEL: store_breg_f64
; CHECK: str {{xzr|d[0-9]+}}, [x0]
; CHECK: str xzr, [x0]
store double 0.0, double* %a
ret void
}
@@ -426,7 +433,7 @@ define i32 @load_breg_sext_shift_offreg_2(i32 %a, i64 %b) {
; Load Scaled Register Offset + Immediate Offset + Sign/Zero extension
define i64 @load_sext_shift_offreg_imm1(i32 %a) {
; CHECK-LABEL: load_sext_shift_offreg_imm1
; CHECK: sbfiz [[REG:x[0-9]+]], x0, #3, #32
; CHECK: sbfiz [[REG:x[0-9]+]], {{x[0-9]+}}, #3, #32
; CHECK-NEXT: ldr {{x[0-9]+}}, {{\[}}[[REG]], #8{{\]}}
%1 = sext i32 %a to i64
%2 = shl i64 %1, 3