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Fix encoding of predicate bits on ARM BX_pred.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135076 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-07-13 20:21:31 +00:00
parent 1337e2b75a
commit d447ac6c8c
1 changed files with 2 additions and 3 deletions
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5
lib/Target/ARM/ARMInstrInfo.td
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@ -1378,9 +1378,8 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
let Inst{3-0} = dst;
}
// For disassembly only.
def BX_pred : AXI<(outs), (ins GPR:$dst, pred:$p), BrMiscFrm, IIC_Br,
"bx$p\t$dst", [/* pattern left blank */]>,
def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
"bx", "\t$dst", [/* pattern left blank */]>,
Requires<[IsARM, HasV4T]> {
bits<4> dst;
let Inst{27-4} = 0b000100101111111111110001;