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https://github.com/c64scene-ar/llvm-6502.git
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Teach LegalizeTypes how to expand and promote CTLZ,
CTTZ and CTPOP. The expansion code differs from that in LegalizeDAG in that it chooses to take the CTLZ/CTTZ count from the Hi/Lo part depending on whether the Hi/Lo value is zero, not on whether CTLZ/CTTZ of Hi/Lo returned 32 (or whatever the width of the type is) for it. I made this change because the optimizers may well know that Hi/Lo is zero and exploit it. The promotion code for CTTZ also differs from that in LegalizeDAG: it uses an "or" to get the right result when the original value is zero, rather than using a compare and select. This also means the value doesn't need to be zero extended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47075 91177308-0d34-0410-b5e6-96231b3b80d8
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Duncan Sands
parent
82f0a09c10
commit
d462ba8539
@ -159,23 +159,26 @@ private:
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// Result Promotion.
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void PromoteResult(SDNode *N, unsigned ResNo);
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SDOperand PromoteResult_UNDEF(SDNode *N);
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SDOperand PromoteResult_Constant(SDNode *N);
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SDOperand PromoteResult_TRUNCATE(SDNode *N);
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SDOperand PromoteResult_INT_EXTEND(SDNode *N);
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SDOperand PromoteResult_CTLZ(SDNode *N);
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SDOperand PromoteResult_CTPOP(SDNode *N);
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SDOperand PromoteResult_CTTZ(SDNode *N);
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SDOperand PromoteResult_FP_ROUND(SDNode *N);
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SDOperand PromoteResult_FP_TO_XINT(SDNode *N);
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SDOperand PromoteResult_SETCC(SDNode *N);
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SDOperand PromoteResult_INT_EXTEND(SDNode *N);
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SDOperand PromoteResult_LOAD(LoadSDNode *N);
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SDOperand PromoteResult_SimpleIntBinOp(SDNode *N);
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SDOperand PromoteResult_SDIV(SDNode *N);
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SDOperand PromoteResult_UDIV(SDNode *N);
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SDOperand PromoteResult_SHL(SDNode *N);
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SDOperand PromoteResult_SRA(SDNode *N);
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SDOperand PromoteResult_SRL(SDNode *N);
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SDOperand PromoteResult_SELECT (SDNode *N);
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SDOperand PromoteResult_SELECT_CC(SDNode *N);
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SDOperand PromoteResult_SETCC(SDNode *N);
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SDOperand PromoteResult_SHL(SDNode *N);
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SDOperand PromoteResult_SimpleIntBinOp(SDNode *N);
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SDOperand PromoteResult_SRA(SDNode *N);
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SDOperand PromoteResult_SRL(SDNode *N);
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SDOperand PromoteResult_TRUNCATE(SDNode *N);
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SDOperand PromoteResult_UDIV(SDNode *N);
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SDOperand PromoteResult_UNDEF(SDNode *N);
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// Operand Promotion.
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bool PromoteOperand(SDNode *N, unsigned OperandNo);
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SDOperand PromoteOperand_ANY_EXTEND(SDNode *N);
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@ -202,18 +205,21 @@ private:
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// Result Expansion.
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void ExpandResult(SDNode *N, unsigned ResNo);
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void ExpandResult_UNDEF (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_Constant (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_BUILD_PAIR (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_MERGE_VALUES(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_ANY_EXTEND (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_ZERO_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_SIGN_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_AssertZext (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_TRUNCATE (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_BUILD_PAIR (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_Constant (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_CTLZ (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_CTPOP (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_CTTZ (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_LOAD (LoadSDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_MERGE_VALUES(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_SIGN_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_TRUNCATE (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_UNDEF (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_ZERO_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_Logical (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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void ExpandResult_BSWAP (SDNode *N, SDOperand &Lo, SDOperand &Hi);
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@ -82,8 +82,12 @@ void DAGTypeLegalizer::ExpandResult(SDNode *N, unsigned ResNo) {
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case ISD::SHL:
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case ISD::SRA:
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case ISD::SRL: ExpandResult_Shift(N, Lo, Hi); break;
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case ISD::CTLZ: ExpandResult_CTLZ(N, Lo, Hi); break;
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case ISD::CTPOP: ExpandResult_CTPOP(N, Lo, Hi); break;
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case ISD::CTTZ: ExpandResult_CTTZ(N, Lo, Hi); break;
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}
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// If Lo/Hi is null, the sub-method took care of registering results etc.
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if (Lo.Val)
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SetExpandedOp(SDOperand(N, ResNo), Lo, Hi);
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@ -615,6 +619,51 @@ void DAGTypeLegalizer::ExpandResult_Shift(SDNode *N,
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#endif
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}
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void DAGTypeLegalizer::ExpandResult_CTLZ(SDNode *N,
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SDOperand &Lo, SDOperand &Hi) {
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// ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
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GetExpandedOp(N->getOperand(0), Lo, Hi);
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MVT::ValueType NVT = Lo.getValueType();
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SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
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DAG.getConstant(0, NVT), ISD::SETNE);
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SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
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SDOperand HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
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Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
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DAG.getNode(ISD::ADD, NVT, LoLZ,
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DAG.getConstant(MVT::getSizeInBits(NVT), NVT)));
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Hi = DAG.getConstant(0, NVT);
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}
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void DAGTypeLegalizer::ExpandResult_CTPOP(SDNode *N,
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SDOperand &Lo, SDOperand &Hi) {
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// ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
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GetExpandedOp(N->getOperand(0), Lo, Hi);
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MVT::ValueType NVT = Lo.getValueType();
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Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
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DAG.getNode(ISD::CTPOP, NVT, Hi));
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Hi = DAG.getConstant(0, NVT);
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}
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void DAGTypeLegalizer::ExpandResult_CTTZ(SDNode *N,
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SDOperand &Lo, SDOperand &Hi) {
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// cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
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GetExpandedOp(N->getOperand(0), Lo, Hi);
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MVT::ValueType NVT = Lo.getValueType();
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SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), Lo,
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DAG.getConstant(0, NVT), ISD::SETNE);
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SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
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SDOperand HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
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Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
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DAG.getNode(ISD::ADD, NVT, HiLZ,
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DAG.getConstant(MVT::getSizeInBits(NVT), NVT)));
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Hi = DAG.getConstant(0, NVT);
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}
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/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
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/// and the shift amount is a constant 'Amt'. Expand the operation.
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@ -70,6 +70,9 @@ void DAGTypeLegalizer::PromoteResult(SDNode *N, unsigned ResNo) {
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case ISD::SELECT: Result = PromoteResult_SELECT(N); break;
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case ISD::SELECT_CC: Result = PromoteResult_SELECT_CC(N); break;
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case ISD::CTLZ: Result = PromoteResult_CTLZ(N); break;
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case ISD::CTPOP: Result = PromoteResult_CTPOP(N); break;
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case ISD::CTTZ: Result = PromoteResult_CTTZ(N); break;
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}
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// If Result is null, the sub-method took care of registering the result.
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@ -265,6 +268,38 @@ SDOperand DAGTypeLegalizer::PromoteResult_SELECT_CC(SDNode *N) {
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N->getOperand(1), LHS, RHS, N->getOperand(4));
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}
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SDOperand DAGTypeLegalizer::PromoteResult_CTLZ(SDNode *N) {
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SDOperand Op = GetPromotedOp(N->getOperand(0));
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MVT::ValueType OVT = N->getValueType(0);
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MVT::ValueType NVT = Op.getValueType();
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// Zero extend to the promoted type and do the count there.
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Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
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// Subtract off the extra leading bits in the bigger type.
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return DAG.getNode(ISD::SUB, NVT, Op,
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DAG.getConstant(MVT::getSizeInBits(NVT) -
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MVT::getSizeInBits(OVT), NVT));
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}
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SDOperand DAGTypeLegalizer::PromoteResult_CTPOP(SDNode *N) {
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SDOperand Op = GetPromotedOp(N->getOperand(0));
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MVT::ValueType OVT = N->getValueType(0);
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MVT::ValueType NVT = Op.getValueType();
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// Zero extend to the promoted type and do the count there.
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return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
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}
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SDOperand DAGTypeLegalizer::PromoteResult_CTTZ(SDNode *N) {
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SDOperand Op = GetPromotedOp(N->getOperand(0));
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MVT::ValueType OVT = N->getValueType(0);
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MVT::ValueType NVT = Op.getValueType();
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// The count is the same in the promoted type except if the original
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// value was zero. This can be handled by setting the bit just off
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// the top of the original type.
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Op = DAG.getNode(ISD::OR, NVT, Op,
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// FIXME: Do this using an APINT constant.
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DAG.getConstant(1UL << MVT::getSizeInBits(OVT), NVT));
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return DAG.getNode(ISD::CTTZ, NVT, Op);
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}
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//===----------------------------------------------------------------------===//
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// Operand Promotion
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@ -1,22 +1,21 @@
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; RUN: llvm-as < %s | llc
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@.str3 = external constant [56 x i8] ; <[56 x i8]*> [#uses=1]
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@.str = internal constant [14 x i8] c"%lld %d %d %d\00"
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define i32 @main() nounwind {
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define i32 @main(i64 %arg) nounwind {
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entry:
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br label %bb30
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bb30: ; preds = %bb30, %entry
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%l.024 = phi i64 [ -10000, %entry ], [ 0, %bb30 ] ; <i64> [#uses=2]
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%tmp37 = tail call i64 @llvm.ctlz.i64( i64 %l.024 ) ; <i64> [#uses=1]
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trunc i64 %tmp37 to i32 ; <i32>:0 [#uses=1]
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%tmp40 = tail call i32 (i8*, ...)* @printf( i8* noalias getelementptr ([56 x i8]* @.str3, i32 0, i32 0), i64 %l.024, i32 %0, i32 0, i32 0 ) nounwind ; <i32> [#uses=0]
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br i1 false, label %bb30, label %bb9.i
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bb9.i: ; preds = %bb30
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%tmp37 = tail call i64 @llvm.ctlz.i64( i64 %arg ) ; <i64> [#uses=1]
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%tmp47 = tail call i64 @llvm.cttz.i64( i64 %arg ) ; <i64> [#uses=1]
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%tmp57 = tail call i64 @llvm.ctpop.i64( i64 %arg ) ; <i64> [#uses=1]
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%tmp38 = trunc i64 %tmp37 to i32 ; <i32>:0 [#uses=1]
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%tmp48 = trunc i64 %tmp47 to i32 ; <i32>:0 [#uses=1]
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%tmp58 = trunc i64 %tmp57 to i32 ; <i32>:0 [#uses=1]
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%tmp40 = tail call i32 (i8*, ...)* @printf( i8* noalias getelementptr ([14 x i8]* @.str, i32 0, i32 0), i64 %arg, i32 %tmp38, i32 %tmp48, i32 %tmp58 ) nounwind ; <i32> [#uses=0]
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ret i32 0
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}
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declare i32 @printf(i8* noalias , ...) nounwind
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declare i64 @llvm.ctlz.i64(i64) nounwind readnone
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declare i64 @llvm.cttz.i64(i64) nounwind readnone
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declare i64 @llvm.ctpop.i64(i64) nounwind readnone
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