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Consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37274 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -217,7 +217,7 @@ public:
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bool isCommutableInstr(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_COMMUTABLE;
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}
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bool isTerminatorInstr(unsigned Opcode) const {
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bool isTerminatorInstr(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_TERMINATOR_FLAG;
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}
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@@ -244,14 +244,14 @@ public:
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/// hasDelaySlot - Returns true if the specified instruction has a delay slot
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/// which must be filled by the code generator.
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bool hasDelaySlot(unsigned Opcode) const {
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bool hasDelaySlot(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
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}
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/// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
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/// custom insertion support when the DAG scheduler is inserting it into a
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/// machine basic block.
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bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
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bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
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}
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