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[mips][microMIPS] Implement 16-bit instructions registers including ZERO instead of S0

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Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17.

Differential Revision: http://reviews.llvm.org/D5780


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222652 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jozef Kolek 2014-11-24 14:25:53 +00:00
parent 39e9ec3049
commit d49e74eaa5
3 changed files with 41 additions and 0 deletions
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12
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -663,6 +663,11 @@ public:
Inst.addOperand(MCOperand::CreateReg(getGPRMM16Reg()));
}
void addGPRMM16AsmRegZeroOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateReg(getGPRMM16Reg()));
}
/// Render the operand to an MCInst as a GPR64
/// Asserts if the wrong number of operands are requested, or the operand
/// is not a k_RegisterIndex compatible with RegKind_GPR
@ -964,6 +969,13 @@ public:
return ((RegIdx.Index >= 2 && RegIdx.Index <= 7)
|| RegIdx.Index == 16 || RegIdx.Index == 17);
}
bool isMM16AsmRegZero() const {
if (!(isRegIdx() && RegIdx.Kind))
return false;
return (RegIdx.Index == 0 ||
(RegIdx.Index >= 2 && RegIdx.Index <= 7) ||
RegIdx.Index == 17);
}
bool isFGRAsmReg() const {
// AFGR64 is $0-$15 but we handle this in getAFGR64()
return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;

12
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
View File

@ -109,6 +109,11 @@ static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
@ -900,6 +905,13 @@ static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
return MCDisassembler::Success;
}
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
return MCDisassembler::Fail;
}
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,

17
lib/Target/Mips/MipsRegisterInfo.td
View File

@ -294,6 +294,14 @@ def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add
// Return Values and Arguments
V0, V1, A0, A1, A2, A3)>;
def GPRMM16Zero : RegisterClass<"Mips", [i32], 32, (add
// Reserved
ZERO,
// Return Values and Arguments
V0, V1, A0, A1, A2, A3,
// Callee save
S1)>;
def GPR64 : RegisterClass<"Mips", [i64], 64, (add
// Reserved
ZERO_64, AT_64,
@ -446,6 +454,11 @@ def GPRMM16AsmOperand : MipsAsmRegOperand {
let PredicateMethod = "isMM16AsmReg";
}
def GPRMM16AsmOperandZero : MipsAsmRegOperand {
let Name = "GPRMM16AsmRegZero";
let PredicateMethod = "isMM16AsmRegZero";
}
def ACC64DSPAsmOperand : MipsAsmRegOperand {
let Name = "ACC64DSPAsmReg";
let PredicateMethod = "isACCAsmReg";
@ -505,6 +518,10 @@ def GPRMM16Opnd : RegisterOperand<GPRMM16> {
let ParserMatchClass = GPRMM16AsmOperand;
}
def GPRMM16OpndZero : RegisterOperand<GPRMM16Zero> {
let ParserMatchClass = GPRMM16AsmOperandZero;
}
def GPR64Opnd : RegisterOperand<GPR64> {
let ParserMatchClass = GPR64AsmOperand;
}