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Do not preset the cc register, the instructions actually use it.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6637 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman
2003-06-05 23:30:27 +00:00
parent 3d194ac26b
commit d4ad1d10bc
1 changed files with 17 additions and 20 deletions
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5
lib/Target/SparcV9/SparcV9.td
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@@ -77,10 +77,8 @@ set isDeprecated = 1 in {
}
#endif
// These instructions are hacked to really represent A.5 instructions,
// but with cc hardcoded to be %fcc0. Hence, they behave like FBPfcc instrs.
// We now make these same opcodes represent the FBPfcc instructions
set op2 = 0b101 in {
set cc = 0b00 in {
def FBA : F2_3<0b1000, "fba">; // Branch always
def FBN : F2_3<0b0000, "fbn">; // Branch never
def FBU : F2_3<0b0111, "fbu">; // Branch on unordered
@@ -98,7 +96,6 @@ set op2 = 0b101 in {
def FBULE : F2_3<0b1110, "fbule">; // Branch unord or < or ==
def FBO : F2_3<0b1111, "fbo">; // Branch on ordered
}
}
// Section A.5: Branch on FP condition codes with prediction - p143
// Not used in the Sparc backend