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Define function MipsInstrInfo::GetInstSizeInBytes, which will be called to
compute the size of basic blocks in a function. Also, define a function which emits a series of instructions to load an immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158429 91177308-0d34-0410-b5e6-96231b3b80d8
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lib/Target/Mips
@ -11,6 +11,7 @@
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//
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//===----------------------------------------------------------------------===//
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#include "MipsAnalyzeImmediate.h"
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#include "MipsInstrInfo.h"
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#include "MipsTargetMachine.h"
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#include "MipsMachineFunction.h"
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@ -505,3 +506,58 @@ ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
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return false;
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}
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/// Return the number of bytes of code the specified instruction may be.
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unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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default:
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return MI->getDesc().getSize();
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case TargetOpcode::INLINEASM: { // Inline Asm: Variable size.
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const MachineFunction *MF = MI->getParent()->getParent();
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const char *AsmStr = MI->getOperand(0).getSymbolName();
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return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
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}
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}
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}
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unsigned
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llvm::Mips::loadImmediate(int64_t Imm, bool IsN64, const TargetInstrInfo &TII,
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MachineBasicBlock& MBB,
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MachineBasicBlock::iterator II, DebugLoc DL,
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bool LastInstrIsADDiu,
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MipsAnalyzeImmediate::Inst *LastInst) {
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MipsAnalyzeImmediate AnalyzeImm;
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unsigned Size = IsN64 ? 64 : 32;
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unsigned LUi = IsN64 ? Mips::LUi64 : Mips::LUi;
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unsigned ZEROReg = IsN64 ? Mips::ZERO_64 : Mips::ZERO;
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unsigned ATReg = IsN64 ? Mips::AT_64 : Mips::AT;
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const MipsAnalyzeImmediate::InstSeq &Seq =
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AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
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MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
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if (LastInst && (Seq.size() == 1)) {
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*LastInst = *Inst;
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return 0;
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}
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// The first instruction can be a LUi, which is different from other
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// instructions (ADDiu, ORI and SLL) in that it does not have a register
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// operand.
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if (Inst->Opc == LUi)
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BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
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.addImm(SignExtend64<16>(Inst->ImmOpnd));
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else
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BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
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.addImm(SignExtend64<16>(Inst->ImmOpnd));
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// Build the remaining instructions in Seq. Skip the last instruction if
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// LastInst is not 0.
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for (++Inst; Inst != Seq.end() - !!LastInst; ++Inst)
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BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
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.addImm(SignExtend64<16>(Inst->ImmOpnd));
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if (LastInst)
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*LastInst = *Inst;
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return Seq.size() - !!LastInst;
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}
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@ -15,6 +15,7 @@
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#define MIPSINSTRUCTIONINFO_H
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#include "Mips.h"
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#include "MipsAnalyzeImmediate.h"
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#include "MipsRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetInstrInfo.h"
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@ -24,12 +25,6 @@
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namespace llvm {
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namespace Mips {
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/// GetOppositeBranchOpc - Return the inverse of the specified
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/// opcode, e.g. turning BEQ to BNE.
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unsigned GetOppositeBranchOpc(unsigned Opc);
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}
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class MipsInstrInfo : public MipsGenInstrInfo {
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MipsTargetMachine &TM;
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bool IsN64;
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@ -109,8 +104,27 @@ public:
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/// Insert nop instruction when hazard condition is found
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virtual void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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/// Return the number of bytes of code the specified instruction may be.
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unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
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};
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namespace Mips {
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/// GetOppositeBranchOpc - Return the inverse of the specified
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/// opcode, e.g. turning BEQ to BNE.
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unsigned GetOppositeBranchOpc(unsigned Opc);
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/// Emit a series of instructions to load an immediate. All instructions
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/// except for the last one are emitted. The function returns the number of
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/// MachineInstrs generated. The opcode-immediate pair of the last
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/// instruction is returned in LastInst, if it is not 0.
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unsigned
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loadImmediate(int64_t Imm, bool IsN64, const TargetInstrInfo &TII,
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MachineBasicBlock& MBB, MachineBasicBlock::iterator II,
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DebugLoc DL, bool LastInstrIsADDiu,
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MipsAnalyzeImmediate::Inst *LastInst);
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}
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}
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#endif
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